公开(公告)号：US10777651B2

公开(公告)日：2020-09-15

申请号：US16201624

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： Yushi Hu ,  John Mark Meldrim ,  Eric Blomiley ,  Everett Allen McTeer ,  Matthew J. King

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

公开(公告)号：US20190206727A1

公开(公告)日：2019-07-04

申请号：US16172218

申请日：2018-10-26

Applicant: Micron Technology, Inc.

Inventor： John B. Matovu ,  David S. Meyaard ,  Gowrisankar Damarla ,  Sri Sai Sivakumar Vegunta ,  Kunal Shrotri ,  Shashank Saraf ,  Kevin R. Gast ,  Jivaan Kishore Jhothiraman ,  Suresh Ramarajan ,  Lifang Xu ,  Rithu K. Bhonsle ,  Rutuparna Narulkar ,  Matthew J. King

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

公开(公告)号：US20250159878A1

公开(公告)日：2025-05-15

申请号：US19022599

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H10B41/30 ,  H01L21/768 ,  H10B41/20 ,  H10B41/47 ,  H10B41/50 ,  H10B43/50

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20250159877A1

公开(公告)日：2025-05-15

申请号：US19022523

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H10B41/30 ,  H01L21/768 ,  H10B41/20 ,  H10B41/47 ,  H10B41/50 ,  H10B43/50

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US12171101B2

公开(公告)日：2024-12-17

申请号：US17822708

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Matthew J. King ,  Jordan D. Greenlee ,  Yongjun J. Hu ,  Tom George ,  Amritesh Rai ,  Sidhartha Gupta ,  Kyle A. Ritter

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/49 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/30 ,  H10B43/40

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US12010847B2

公开(公告)日：2024-06-11

申请号：US17691993

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Matthew J. King ,  John D. Hopkins ,  M. Jared Barclay

IPC: H10B43/27 ,  H01L23/48 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/481 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.

公开(公告)号：US20240112734A1

公开(公告)日：2024-04-04

申请号：US18529731

申请日：2023-12-05

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Albert Fayrushin ,  Matthew J. King ,  Madison D. Drake

IPC: G11C16/04 ,  H01L29/66 ,  H01L29/78 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/66795 ,  H01L29/7851 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.

公开(公告)号：US11887667B2

公开(公告)日：2024-01-30

申请号：US17397603

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Albert Fayrushin ,  Matthew J. King ,  Madison D Drake

IPC: G11C16/04 ,  H01L29/66 ,  H01L29/78 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/66795 ,  H01L29/7851 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.

公开(公告)号：US11805645B2

公开(公告)日：2023-10-31

申请号：US16542645

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Andrew Li ,  Adam W. Saxler ,  Kunal Shrotri ,  Erik R. Byers ,  Matthew J. King ,  Diem Thy N. Tran ,  Wei Yeeng Ng ,  Anish A. Khandekar

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/285 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02631 ,  H01L21/02636 ,  H01L21/28568 ,  H10B41/27

Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11800717B2

公开(公告)日：2023-10-24

申请号：US17661659

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H01L21/76 ,  H01L29/06 ,  H10B43/27 ,  H01L21/762

CPC classification number: H10B43/27 ,  H01L21/76224 ,  H01L29/0649

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.