公开(公告)号：US07943517B2

公开(公告)日：2011-05-17

申请号：US11877243

申请日：2007-10-23

申请人： Junichi Koike ,  Makoto Wada ,  Shingo Takahashi ,  Noriyoshi Shimizu ,  Hideki Shibata ,  Satoshi Nishikawa ,  Takamasa Usui ,  Hayato Nasu ,  Masaki Yoshimaru

发明人： Junichi Koike ,  Makoto Wada ,  Shingo Takahashi ,  Noriyoshi Shimizu ,  Hideki Shibata ,  Satoshi Nishikawa ,  Takamasa Usui ,  Hayato Nasu ,  Masaki Yoshimaru

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.

摘要翻译： 一种制造半导体器件的方法，包括在设置在半导体衬底上的层间绝缘膜中形成开口，形成含有预定金属元素的辅助膜以覆盖开口的内表面，形成主膜以填充开口 在形成辅助膜之后，主膜含有用作互连主层的材料的Cu，并且在形成主膜之前或之后进行热处理，从而扩散辅助膜的预定金属元素 在面向辅助膜的层间绝缘膜的表面上，以在开口内的层间绝缘膜上形成阻挡膜，所述阻挡膜以预定的金属元素与成分元素为主要成分， 的层间绝缘膜。

公开(公告)号：US07816279B2

公开(公告)日：2010-10-19

申请号：US12369297

申请日：2009-02-11

申请人： Michie Sunayama ,  Yoshiyuki Nakao ,  Noriyoshi Shimizu

发明人： Michie Sunayama ,  Yoshiyuki Nakao ,  Noriyoshi Shimizu

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L23/53295 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/914 ,  H01L2924/00

摘要： A semiconductor device includes a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.

摘要翻译： 半导体器件包括设置在半导体衬底上的第一导体; 设置在所述半导体衬底上和所述第一导体上的含氧绝缘膜，所述绝缘膜具有延伸到所述第一导体的接触孔和与所述接触孔的上部连接的沟槽; 设置在所述接触孔的侧表面上的氧化锆膜和所述沟槽的侧表面和底表面; 在所述接触孔内部和所述沟槽内部设置在所述氧化锆膜上的锆膜; 以及由嵌入接触孔并进入沟槽的Cu构成的第二导体。

公开(公告)号：US07803642B2

公开(公告)日：2010-09-28

申请号：US12548851

申请日：2009-08-27

申请人： Michie Sunayama ,  Noriyoshi Shimizu ,  Masaki Haneda

发明人： Michie Sunayama ,  Noriyoshi Shimizu ,  Masaki Haneda

IPC分类号： G01R31/26

CPC分类号： C25D7/123 ,  C25D5/50 ,  H01L21/2885 ,  H01L21/76877 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A technology for analyzing and evaluating of a change of impurity content distribution at the heat treatment of electrodeposited copper film. There is provided a method of evaluating a semiconductor device, comprising providing an electrodeposited copper film formed while causing the deposition current to transit between the first state of current density and the second state of current density so as to attain a desired impurity content distribution and carrying out analysis and evaluation of any impurity diffusion from a change of impurity content distribution in the electrodeposited copper film between before and after heat treatment.

摘要翻译： 一种用于分析和评估电沉积铜膜热处理中杂质含量分布变化的技术。 提供了一种评估半导体器件的方法，包括提供形成的电沉积铜膜，同时使沉积电流在第一电流密度状态和第二电流密度之间转移，从而获得所需的杂质含量分布和携带 对热处理前后电沉积铜膜中杂质含量分布变化的任何杂质扩散进行分析和评估。

公开(公告)号：US20080236662A1

公开(公告)日：2008-10-02

申请号：US11953457

申请日：2007-12-10

申请人： Sumihiro Ichikawa ,  Koji Takei ,  Noriyoshi Shimizu ,  Yasunari Suzuki ,  Ryo Fukasawa ,  Daisuke Matono ,  Yuichiro Shimizu

发明人： Sumihiro Ichikawa ,  Koji Takei ,  Noriyoshi Shimizu ,  Yasunari Suzuki ,  Ryo Fukasawa ,  Daisuke Matono ,  Yuichiro Shimizu

IPC分类号： H01L31/042 ,  H01L31/18

CPC分类号： H01G9/2068 ,  H01G9/2031 ,  H01G9/2059 ,  Y02E10/542 ,  Y02P70/521

摘要： In a solar cell module in which a plurality of dye sensitized solar cells is arranged on a plane basis and is connected in series with an intercell region interposed therebetween, a first transparent substrate, a first transparent conductive film, a dye carrying oxide semiconductor layer, an electrolyte layer, a catalyst layer, a second transparent conductive film and a second transparent substrate are laminated, an insulating barrier seals cells on both sides thereof in fluid tightness and insulates them in the intercell region, an electrode connecting portion provided in a central part in a vertical direction of the insulating barrier connects an extended portion of the first transparent conductive film of one of the cells on the both sides to that of a second transparent conductive film of the other cell, and the electrode connecting portion penetrates through at least one of the first transparent substrate and the second transparent substrate in the vertical direction and is thus exposed.

摘要翻译： 在其中多个染料敏化太阳能电池被布置在基板上并与其间插入的电池间串联连接的太阳能电池模块中，第一透明基板，第一透明导电膜，载染氧化物半导体层， 电解质层，催化剂层，第二透明导电膜和第二透明基板层叠，绝缘隔离件两侧以流体密封的方式密封电池并将其绝缘在电池间区域中，电极连接部分设置在中心部分 在绝缘阻挡件的垂直方向上，将两侧的一个单元的第一透明导电膜的延伸部分与另一个单元的第二透明导电膜的第一透明导电膜的延伸部分连接，并且电极连接部分穿过至少一个 的第一透明基板和第二透明基板，因此为e 放置。

公开(公告)号：US07414309B2

公开(公告)日：2008-08-19

申请号：US11593538

申请日：2006-11-07

申请人： Kiyoshi Oi ,  Noriyoshi Shimizu ,  Yasuyoshi Horikawa

发明人： Kiyoshi Oi ,  Noriyoshi Shimizu ,  Yasuyoshi Horikawa

IPC分类号： H01L23/12 ,  H01L21/00

CPC分类号： H01L24/82 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82375 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/49204 ,  H01L2924/00014 ,  H01L2924/00

摘要： An encapsulated electronic part packaging structure includes a step of mounting an electronic part having a connection terminal and a passivating film to cover the connection terminal, mounted on a body to direct the connection terminal upward. An insulating layer is formed to cover the electronic part, and a via hole is formed in a portion of the passivating film and the insulating layer on the connection terminal to expose the connection terminal. A wiring pattern, which is connected electrically to the connection terminal via the via hole, is formed on the insulating layer.

摘要翻译： 封装的电子部件封装结构包括安装具有连接端子和钝化膜的电子部件以覆盖安装在主体上以将连接端子向上引导的连接端子的步骤。 形成绝缘层以覆盖电子部件，并且在钝化膜的一部分和连接端子上的绝缘层上形成通孔以露出连接端子。 在绝缘层上形成有经由通路孔与连接端子电连接的布线图案。

公开(公告)号：US07358180B2

公开(公告)日：2008-04-15

申请号：US10927006

申请日：2004-08-27

申请人： Hisaya Sakai ,  Noriyoshi Shimizu

发明人： Hisaya Sakai ,  Noriyoshi Shimizu

IPC分类号： H01L21/28

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76865 ,  H01L21/76873

摘要： A micronized wiring structure is obtained by optimizing film forming modes of barrier metal films as being adapted respectively to a via-hole and a wiring groove, wherein sputtering processes are adopted herein, which are specifically the multi-step sputtering process for formation of the barrier metal film over the via-hole, and the one-step, low-power sputtering process for formation of the barrier metal film over the wiring groove, to thereby realize improved electric characteristics such as via-hole resistance and wiring resistance, and improved wiring reliabilities such as Cu filling property and electro-migration resistance.

公开(公告)号：US20070134899A1

公开(公告)日：2007-06-14

申请号：US11366511

申请日：2006-03-03

申请人： Tsuyoshi Kanki ,  Nobuyuki Ohtsuka ,  Hisaya Sakai ,  Noriyoshi Shimizu

发明人： Tsuyoshi Kanki ,  Nobuyuki Ohtsuka ,  Hisaya Sakai ,  Noriyoshi Shimizu

IPC分类号： H01L21/44

CPC分类号： H01L21/3105 ,  H01L21/02063 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828

摘要： (a) A recess is formed through an insulating film formed over a semiconductor substrate. (b) After the recess is formed, a temperature of the substrate is raised to 300° C. or higher at a temperature rising rate of 10° C./s or slower and a first degassing process is executed. (c) After the first degassing process, a conductive film is deposited on the insulating film, the conductive film being embedded in the recess. (d) The deposited conductive film is polished until the insulating film is exposed. It is possible to suppress occurrence of defects during CMP to be performed after a conductive member is deposited on the surface of the insulating film having a recess formed therethrough.

摘要翻译： （a）通过在半导体衬底上形成的绝缘膜形成凹部。 （b）在形成凹部之后，以10℃/秒以下的升温速度将基板的温度升高至300℃以上，进行第一脱气处理。 （c）在第一脱气处理之后，在绝缘膜上沉积导电膜，导电膜嵌入凹部中。 （d）抛光沉积的导电膜直至暴露绝缘膜。 在导电构件沉积在具有通过其形成的凹部的绝缘膜的表面上之后，可以抑制在CMP期间发生的缺陷。

公开(公告)号：US07211519B2

公开(公告)日：2007-05-01

申请号：US11094578

申请日：2005-03-31

申请人： Yukio Takigawa ,  Noriyoshi Shimizu ,  Toshiya Suzuki ,  Hajime Kawabe

发明人： Yukio Takigawa ,  Noriyoshi Shimizu ,  Toshiya Suzuki ,  Hajime Kawabe

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/4763

CPC分类号： H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3143 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829

摘要： After an SiC film (4), an SiO2 film (5) and a silicon nitride film (6) are formed sequentially on an organic low dielectric constant film (3), by performing O2 plasma processing to a surface of the silicon nitride film (6), an oxide layer (7) is formed on the surface of the silicon nitride film (6). Then, a wiring trench pattern is formed on the silicon nitride film (6) and the oxide layer (7), and a resin layer (10) on which a via hole pattern is formed is formed. Subsequently, a portion of the oxide layer (7) exposed from the resin layer (10) is removed along with unnecessary particles.

摘要翻译： 在SiC膜（4）之后，依次在有机低介电常数膜（3）上形成SiO 2膜（5）和氮化硅膜（6），通过执​​行O < 对氮化硅膜（6）的表面进行等离子体处理，在氮化硅膜（6）的表面上形成氧化物层（7）。 然后，在氮化硅膜（6）和氧化物层（7）上形成布线沟槽图案，形成通孔图案的树脂层（10）。 随后，从树脂层（10）露出的氧化物层（7）的一部分与不需要的颗粒一起除去。

公开(公告)号：US07173337B2

公开(公告)日：2007-02-06

申请号：US11035745

申请日：2005-01-18

申请人： Kenichi Watanabe ,  Noriyoshi Shimizu ,  Takashi Suzuki

发明人： Kenichi Watanabe ,  Noriyoshi Shimizu ,  Takashi Suzuki

IPC分类号： H01L23/48

CPC分类号： H01L21/76811 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a second insulating film formed on a substantially flat surface, on which a surface of a first wiring and a surface of a first insulating film are continued, to cover the first wiring, a wiring trench formed in the second insulating film, connection holes formed in the second insulating film to extend from the wiring trench to the first wiring, dummy connection holes formed in the second insulating film to extend from the wiring trench to a non-forming region of the first wiring, and a second wiring buried in the connection holes and the wiring trench to be connected electrically to the first wiring and also buried in the dummy connection holes, and formed such that a surface of the second wiring and a surface of the second insulating film constitute a substantially flat surface.

摘要翻译： 一种半导体器件，包括形成在第一布线的表面和第一绝缘膜的表面上的基本上平坦的表面上的第二绝缘膜，以覆盖第一布线;形成在第二绝缘膜中的布线沟槽， 在第二绝缘膜上形成的连接孔从布线沟槽延伸到第一布线，形成在第二绝缘膜中的虚拟连接孔从布线沟槽延伸到第一布线的非形成区域，第二布线埋入 在与第一布线电连接并连接在虚拟连接孔中的连接孔和布线沟槽中，并且形成为使得第二布线的表面和第二绝缘膜的表面构成基本平坦的表面。

公开(公告)号：US20060189115A1

公开(公告)日：2006-08-24

申请号：US11407920

申请日：2006-04-21

申请人： Hisaya Sakai ,  Noriyoshi Shimizu

发明人： Hisaya Sakai ,  Noriyoshi Shimizu

IPC分类号： H01L21/3205

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76865 ,  H01L21/76873

摘要： After a via hole (102) to connect a lower wiring (101) and an upper wiring not shown is formed in an insulating film (103) using an etching stopper film (104) and a hard mask (105), a base film (106) made from Ta is formed over the insulating film (103) so as to cover an inner wall of the via hole (102) by a one-step low-power bias sputtering method of the present invention. Thus, the base film (106) with a thin and uniform film thickness covering a region from an inner wall surface of the via hole (102) to the insulating film (103) is obtained. This makes it possible to form the base film thin and uniformly over the inner wall surface, that is, from a sidewall surface to a bottom surface, of the opening without causing any disadvantage in terms of wiring formation by relatively simple steps, thereby realizing a highly reliable ultra-fine wiring structure.

摘要翻译： 在使用蚀刻停止膜（104）和硬掩模（105）的绝缘膜（103）中形成用于连接下布线（101）和未示出的上布线的通孔（102），基膜 106）形成在绝缘膜（103）上，以便通过本发明的一步低功率偏压溅射法覆盖通孔（102）的内壁。 因此，可以获得覆盖从通孔（102）的内壁面到绝缘膜（103）的区域的薄且均匀的薄膜厚度的基膜（106）。 这使得可以在开口的内壁表面，即从侧壁表面到底表面上均匀地形成基膜，而不会通过相对简单的步骤在布线形成方面造成任何缺点，从而实现 高度可靠的超细线路结构。