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209 条记录 (耗时 0.065 秒)

    ELECTRICALLY PROGRAMMABLE FUSE AND FABRICATION METHOD
    74.
    发明申请
    ELECTRICALLY PROGRAMMABLE FUSE AND FABRICATION METHOD 有权
    电可编程保险丝和制造方法

    公开(公告)号：US20100038747A1

    公开(公告)日：2010-02-18

    申请号：US12192387

    申请日：2008-08-15

    申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Joseph M. Lukaitis ,  Ping-Chuan Wang

    发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Joseph M. Lukaitis ,  Ping-Chuan Wang

    IPC分类号： H01L21/768 ,  H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.

    摘要翻译： 电可编程保险丝包括阳极，阴极和导电地连接阴极与阳极的熔断体，其可通过施加编程电流来编程。 阳极和熔丝链路各自包括形成在多晶硅层上的多晶硅层和硅化物层，并且阴极包括多晶硅层和形成在阴极的多晶硅层的预定部分上的部分硅化物层，其位于阴极附近 阴极和熔断体连接处的连接处。

    Interconnect structure having enhanced electromigration reliability and a method of fabricating same
    75.
    发明授权
    Interconnect structure having enhanced electromigration reliability and a method of fabricating same 有权
    具有增强的电迁移可靠性的互连结构及其制造方法

    公开(公告)号：US07569475B2

    公开(公告)日：2009-08-04

    申请号：US11560044

    申请日：2006-11-15

    申请人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Yun-Yu Wang

    发明人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Yun-Yu Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76847 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the “U-shaped” EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.

    摘要翻译： 提供了具有改进的电迁移（EM）可靠性的互连结构。 本发明的互连结构避免了通过将至少部分地在金属互连内部结合EM防止衬垫而由EM故障引起的电路死路。 在一个实施例中，提供了一种“U形”防EM衬垫，其与导电材料与电介质材料分离的扩散屏障相邻。 在另一个实施例中，空间位于“U形”EM防护衬垫和扩散阻挡层之间。 在另一个实施例中，提供了一个与扩散阻挡件相邻的水平EM衬垫。 在又一个实施例中，在水平EM衬垫和扩散阻挡层之间存在一个空间。

    METHOD AND APPARATUS FOR DYNAMIC CHARACTERIZATION OF RELIABILITY WEAROUT MECHANISMS
    76.
    发明申请
    METHOD AND APPARATUS FOR DYNAMIC CHARACTERIZATION OF RELIABILITY WEAROUT MECHANISMS 失效
    用于动态表征可靠性磨损机制的方法和装置

    公开(公告)号：US20090167336A1

    公开(公告)日：2009-07-02

    申请号：US11968444

    申请日：2008-01-02

    申请人： Giuseppe La Rosa ,  Kevin Kolvenbach ,  Ping-Chuan Wang ,  Stephen D. Wyatt

    发明人： Giuseppe La Rosa ,  Kevin Kolvenbach ,  Ping-Chuan Wang ,  Stephen D. Wyatt

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2858 ,  G01R31/2856

    摘要： A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.

    摘要翻译： 公开了用于动态表征可靠性损耗机制的方法和装置。 该系统包括结合被测器件的集成电路，用于以第一预定时间间隔向待测器件输入波形的结构，用于禁止向被测器件输入波形的结构，用于测量一个 或更多的基本参数，以及在不受基于一个或多个测量的基本参数的恢复效果的影响下计算被测设备的老化估计的结构。 压力和测量之间的时间被精确控制，提供可重复的实验，并且用于最小化由恢复效果引起的测量误差。

    LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES
    77.
    发明申请
    LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES 审中-公开
    在半导体器件中的横向电流承载能力改进

    公开(公告)号：US20080308940A1

    公开(公告)日：2008-12-18

    申请号：US12198196

    申请日：2008-08-26

    申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： H01L23/522

    CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

    摘要翻译： 半导体结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

    Structure and method for thermally stressing or testing a semiconductor device
    79.
    发明授权
    Structure and method for thermally stressing or testing a semiconductor device 有权
    用于热应力或测试半导体器件的结构和方法

    公开(公告)号：US07375371B2

    公开(公告)日：2008-05-20

    申请号：US11307324

    申请日：2006-02-01

    申请人： Giuseppe La Rosa ,  Kevin W. Kolvenbach ,  John Greg Massey ,  Ping-Chuan Wang ,  Kai Xiu

    发明人： Giuseppe La Rosa ,  Kevin W. Kolvenbach ,  John Greg Massey ,  Ping-Chuan Wang ,  Kai Xiu

    IPC分类号： H01L23/58 ,  H01L29/10 ,  G01R31/02

    CPC分类号： G01R31/2856

    摘要： A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists essentially of a semiconductor material included in the active semiconductor area. Conductive isolation between the first region and the diffusion heater is achieved through use of a separating gate. The separating gate overlies an intermediate region of the active semiconductor area between the first region and the diffusion heater and the separating gate is biasable to conductively isolate the first region from the diffusion heater.

    摘要翻译： 提供了一种在衬底的连续有源半导体区域中包括至少一个半导体器件和扩散加热器的结构。 一个或多个半导体器件设置在有源半导体区域的第一区域中，并且扩散加热器邻近设置，其主要由包含在有源半导体区域中的半导体材料组成。 通过使用分离栅极实现第一区域和扩散加热器之间的导电隔离。 分离栅极覆盖在第一区域和扩散加热器之间的有源半导体区域的中间区域，并且分离栅极可偏置以将第一区域与扩散加热器导电隔离。

    Detection of residual liner materials after polishing in damascene process
    80.
    发明授权
    Detection of residual liner materials after polishing in damascene process 失效
    在镶嵌工艺中抛光后残留衬垫材料的检测

    公开(公告)号：US07361584B2

    公开(公告)日：2008-04-22

    申请号：US10904329

    申请日：2004-11-04

    申请人： Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Stephen K. Loh ,  Ping-Chuan Wang

    发明人： Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Stephen K. Loh ,  Ping-Chuan Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/7688 ,  H01L22/24 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.

    摘要翻译： 用于在镶嵌工艺中抛光之后检测残留衬垫材料的方法和结构包括：包括衬底的集成电路; 介电层; 电介质层上的标记层; 标记层和电介质层上的衬垫; 以及在所述衬里上的金属层，其中所述标记层包括紫外线可检测材料，其在通过紫外线激发时表示在所述标记层上不存在所述金属层和所述衬垫。 此外，标记层包括与电介质层分离的层。 另外，紫外线可检测材料包括荧光材料或磷光材料。