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    PERFORMING MEMORY DATA SCRUBBING OPERATIONS IN PROCESSOR-BASED MEMORY IN RESPONSE TO PERIODIC MEMORY CONTROLLER WAKE-UP PERIODS
    73.
    发明申请
    PERFORMING MEMORY DATA SCRUBBING OPERATIONS IN PROCESSOR-BASED MEMORY IN RESPONSE TO PERIODIC MEMORY CONTROLLER WAKE-UP PERIODS 有权
    在基于处理器的存储器中对存储器控制器唤醒周期进行响应的存储器数据存储器操作

    公开(公告)号：US20160246679A1

    公开(公告)日：2016-08-25

    申请号：US14627268

    申请日：2015-02-20

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun Kim ,  Sungryul Kim ,  Jung Pill Kim

    IPC: G06F11/14 ,  G06F12/02

    CPC classification number: G06F11/1402 ,  G06F11/106 ,  G06F12/023 ,  G06F12/0238 ,  G06F2201/805 ,  G06F2212/7205 ,  Y02D10/13

    Abstract: Aspects of the disclosure involve memory data scrubber circuits configured to perform memory data scrubbing operations in a processor-based memory to provide data error correction in response to periodic memory controller wake-up periods. Memory data scrubbing is performed to correct errors in data words stored in memory. Memory data scrubbing is initiated in the memory to conserve power in response to periodic memory controller wake-up periods during processor idle periods. Further, in certain aspects disclosed herein, the memory data scrubber circuit is provided as a separate system outside of the memory controller in the memory system. In this manner, power consumption can be further reduced, because the memory data scrubber circuit can continue with memory data scrubbing operations in the memory independent of the memory controller operation, and after the memory controller access commands issued during the wake-up period are completed and the memory controller is powered-down.

    Abstract translation: 本公开的方面涉及被配置为在基于处理器的存储器中执行存储器数据擦除操作的存储器数据擦除器电路，以响应于周期性存储器控制器唤醒周期提供数据错误校正。 执行存储器数据擦除以校正存储在存储器中的数据字中的错误。 存储器数据擦除在存储器中启动，以节省处理器空闲周期内的周期性存储器控制器唤醒周期的功率。 此外，在本文公开的某些方面，存储器数据洗涤器电路作为存储器系统中的存储器控​​制器外部的单独系统提供。 以这种方式，由于存储器数据擦除器电路能够独立于存储器控制器操作，并且在完成唤醒期间发出的存储器控​​制器访问命令之后，可以继续存储器数据擦除操作，从而能够进一步降低功耗。 并且内存控制器掉电。

    SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY
    75.
    发明申请
    SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY 有权
    电阻记忆体中的参考电平的系统和方法

    公开(公告)号：US20160125926A1

    公开(公告)日：2016-05-05

    申请号：US14992753

    申请日：2016-01-11

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/004 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0042 ,  G11C2013/0054

    Abstract: A method includes, at a resistive memory device, determining an average effective reference resistance level based on a first effective reference resistance and a second effective reference resistance. The first effective reference resistance is based on a first set of reference cells of the resistive memory device and the second effective reference resistance is based on a second set of reference cells of the resistive memory device. The method includes trimming a reference resistance at least partially based on the average effective reference resistance level. Trimming the reference resistance includes, in response to determining that the first effective reference resistance is not substantially equal to the average effective reference resistance level, modifying one or more states of one or more magnetic tunnel junction devices associated with the first effective reference resistance.

    Abstract translation: 一种方法包括在电阻式存储器件中，基于第一有效参考电阻和第二有效参考电阻来确定平均有效参考电阻电平。 第一有效参考电阻基于电阻性存储器件的第一组参考单元，第二有效参考电阻基于电阻式存储器件的第二组参考单元。 该方法包括至少部分地基于平均有效参考电阻电平来修整参考电阻。 响应于确定第一有效参考电阻基本上不等于平均有效参考电阻电平，修整参考电阻包括修改与第一有效参考电阻相关联的一个或多个磁性隧道结装置的一个或多个状态。

    Refresh scheme for memory cells with next bit table
    76.
    发明授权
    Refresh scheme for memory cells with next bit table 有权
    具有下一位表的存储单元的刷新方案

    公开(公告)号：US09230634B2

    公开(公告)日：2016-01-05

    申请号：US14276452

    申请日：2014-05-13

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Jungwon Suh ,  Xiangyu Dong

    IPC: G06F12/00 ,  G11C11/406 ,  G06F12/02

    CPC classification number: G11C11/406 ,  G06F12/0207 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

    Abstract: A memory refresh control technique allows flexible internal refresh rates based on an external 1× refresh rate and allows skipping a refresh cycle for strong memory rows based on the external 1× refresh rate. A memory controller performs a memory refresh by reading a refresh address from a refresh address counter, reading a weak address from a weak address table and generating a next weak address value based at least in part on a next bit sequence combined with the weak address. The memory controller compares the refresh address to the weak address and to the next weak address value. Based on the comparison, the memory controller selects between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address.

    Abstract translation: 存储器刷新控制技术允许基于外部1×刷新率的灵活的内部刷新率，并允许基于外部1×刷新率跳过强存储器行的刷新周期。 存储器控制器通过从刷新地址计数器读取刷新地址，从弱地址表读取弱地址并且至少部分地基于与弱地址组合的下一个比特序列产生下一个弱地址值来执行存储器刷新。 存储器控制器将刷新地址与弱地址和下一个弱地址值进行比较。 基于比较，存储器控制器在跳过刷新周期，刷新刷新地址，刷新弱地址以及刷新刷新地址和弱地址之间进行选择。

    NMOS-offset canceling current-latched sense amplifier
    78.
    发明授权
    NMOS-offset canceling current-latched sense amplifier 有权
    NMOS偏移消除电流锁存读出放大器

    公开(公告)号：US09111623B1

    公开(公告)日：2015-08-18

    申请号：US14179115

    申请日：2014-02-12

    Applicant: QUALCOMM INCORPORATED ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Taehui Na ,  Ji-su Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0054

    Abstract: A resistive memory sensing method includes sensing outputs of an offset-cancelling dual stage sensing circuit (OCDS-SC) by an NMOS offset-cancelling current latched sense amplifier circuit (NOC-CLSA). The NOC-CLSA is configured with a reduced input capacitance and a reduced offset voltage. Input transistors of the NOC-CLSA are coupled between latch circuitry and ground. A first phase output of the OCDS-SC is stored by the NOC-CLSA during a pre-charge step of the NOC-CLSA operation. A second phase output of the OCDS-SC is stored by the NOC-CLSA during an offset-cancelling step of the NOC-CLSA operation. By pipelining the OCDS-SC and NOC-CLSA, a sensing delay penalty of the OCDS-SC is overcome.

    Abstract translation: 电阻式存储器感测方法包括通过NMOS偏移消除电流锁存读出放大器电路（NOC-CLSA）来感测偏移消除双级感测电路（OCDS-SC）的输出。 NOC-CLSA配置有降低的输入电容和降低的失调电压。 NOC-CLSA的输入晶体管耦合在锁存电路和地之间。 在NOC-CLSA操作的预充电步骤期间，OCDS-SC的第一相输出由NOC-CLSA存储。 在NOC-CLSA操作的偏移消除步骤期间，OCDS-SC的第二相输出由NOC-CLSA存储。 通过流水线OCDS-SC和NOC-CLSA，克服了OCDS-SC的感测延迟损失。

    SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION
    79.
    发明申请
    SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION 有权
    感应放大器偏置电压降低

    公开(公告)号：US20150022264A1

    公开(公告)日：2015-01-22

    申请号：US13947144

    申请日：2013-07-22

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim ,  Daeik D. Kim

    IPC: G01R31/28 ,  H03F1/00

    CPC classification number: G01R31/2851 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/14 ,  G11C29/44 ,  G11C29/46

    Abstract: A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.

    Abstract translation: 电路包括响应于存储测试码的多个锁存器的多个晶体管。 电路还包括耦合到数据单元并耦合到读出放大器的第一位线。 电路还包括耦合到参考单元并耦合到读出放大器的第二位线。 来自一组多个晶体管的电流经由第一位线被施加到数据单元。 基于测试代码来确定多个晶体管的集合。 电路还包括耦合到第一位线和第二位线的测试模式参考电路。

    SYSTEM AND METHOD OF SENSING A MEMORY CELL
    80.
    发明申请
    SYSTEM AND METHOD OF SENSING A MEMORY CELL 有权
    感知记忆细胞的系统和方法

    公开(公告)号：US20140269031A1

    公开(公告)日：2014-09-18

    申请号：US13835251

    申请日：2013-03-15

    Applicant: QUALCOMM INCORPORATED ,  Industry-Academic Cooperation Foundation, Yonsei

    Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Seung H. Kang ,  Jung Pill Kim

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/065 ,  G11C11/1693 ,  G11C13/004 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2207/002

    Abstract: A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage.

    Abstract translation: 一种方法包括感测数据单元的状态以产生数据电压。 数据单元的状态对应于数据单元的基于可编程电阻的存储元件的状态。 该方法还包括感测参考单元的状态以产生参考电压。 通过公共感测路径检测数据信元的状态和参考信元的状态。 该方法还包括基于数据电压和参考电压确定数据单元的逻辑值。

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