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108 条记录 (耗时 0.042 秒)

    Threshold voltage improvement employing fluorine implantation and adjustment oxide layer
    71.
    发明授权
    Threshold voltage improvement employing fluorine implantation and adjustment oxide layer 有权
    使用氟注入和调整氧化物层的阈值电压改善

    公开(公告)号：US07893502B2

    公开(公告)日：2011-02-22

    申请号：US12465908

    申请日：2009-05-14

    申请人： Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Jin-Ping Han ,  Yong Meng Lee

    发明人： Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Jin-Ping Han ,  Yong Meng Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807

    摘要： An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.

    摘要翻译： 可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。 形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。 将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。 在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。 外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。

    STRUCTURE AND METHOD TO IMPROVE SHORT CHANNEL EFFECTS IN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS
    73.
    发明申请
    STRUCTURE AND METHOD TO IMPROVE SHORT CHANNEL EFFECTS IN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS 审中-公开
    在金属氧化物半导体场效应晶体管中改善短路通道效应的结构和方法

    公开(公告)号：US20080121985A1

    公开(公告)日：2008-05-29

    申请号：US11557145

    申请日：2006-11-07

    申请人： Xiangdong Chen ,  Dae-Gyu Park ,  Jae-Yoon Yoo

    发明人： Xiangdong Chen ,  Dae-Gyu Park ,  Jae-Yoon Yoo

    IPC分类号： H01L27/088 ,  H01L21/04 ,  H01L29/78 ,  H01L21/77

    CPC分类号： H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

    摘要： Disclosed are embodiments of improved MOSFET and CMOS structures that provides for increased control over short channel effects. Also disclosed are embodiments of associated methods of forming these structures. The embodiments suppress short channel effects by incorporating buried isolation regions into a transistor below source/drain extension regions and between deep source/drain regions and the channel region and, particularly, between deep source/drain regions and the halo regions. Buried isolation regions between the deep source/drain regions and the channel region minimize drain induced barrier lowering (DIBL) as well as punch through. Additionally, because the deep source/drain regions and halo regions are separated by the buried isolation regions, side-wall junction capacitance and junction leakage are also minimized.

    摘要翻译： 公开了改进的MOSFET和CMOS结构的实施例，其提供对短沟道效应的增加的控制。 还公开了形成这些结构的相关方法的实施例。 这些实施例通过将掩埋隔离区域并入到源极/漏极延伸区域之下以及深源极/漏极区域和沟道区域之间，特别是在深源极/漏极区域和晕圈区域之间的晶体管中来抑制短沟道效应。 在深源极/漏极区域和沟道区域之间的埋置隔离区域最小化漏极引起的屏障降低（DIBL）以及穿通。 此外，由于深源极/漏极区域和晕圈区域被掩埋隔离区域分开，所以侧壁结电容和结漏电也被最小化。

    Gate electrode forming methods using conductive hard mask
    75.
    发明授权
    Gate electrode forming methods using conductive hard mask 失效
    使用导电硬掩模的栅电极形成方法

    公开(公告)号：US07084024B2

    公开(公告)日：2006-08-01

    申请号：US10711642

    申请日：2004-09-29

    申请人： Oleg Gluschenkov ,  Dae-Gyu Park

    发明人： Oleg Gluschenkov ,  Dae-Gyu Park

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28079 ,  H01L21/32139 ,  H01L21/823842 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518

    摘要： Methods related to formation of a gate electrode are disclosed that employ a conductive hard mask as a protective layer during a photoresist removal process. In preferred embodiments, the conductive hard mask includes a metal containing conductor or a metal silicide. The invention prevents process damage on the gate dielectric during wet and/or dry resist strip, and since the conductive hard mask cannot be etched in typical resist strip chemistries, the invention also protects a metal electrode under the hard mask. The steps disclosed allow creation of a multiple work function metal gate electrode, or a mixed metal and polysilicon gate electrode, which do not suffer from the problems of the related art.

    摘要翻译： 公开了在光致抗蚀剂去除过程中使用导电硬掩模作为保护层的与栅电极的形成有关的方法。 在优选实施例中，导电硬掩模包括含金属的导体或金属硅化物。 本发明防止了在湿式和/或干式抗蚀剂条带期间对栅极电介质的工艺损伤，并且由于导电硬掩模不能在典型的抗蚀剂条纹化学中被蚀刻，本发明还保护硬掩模下面的金属电极。 所公开的步骤允许创建不具有现有技术问题的多功能金属栅电极或混合金属和多晶硅栅电极。

    Temperature stable metal nitride gate electrode
    76.
    发明授权
    Temperature stable metal nitride gate electrode 有权
    温度稳定的金属氮化物栅电极

    公开(公告)号：US07023064B2

    公开(公告)日：2006-04-04

    申请号：US10710063

    申请日：2004-06-16

    申请人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

    发明人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

    摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

    摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

    Gate structure with high K dielectric
    77.
    发明授权
    Gate structure with high K dielectric 有权
    具有高K电介质的栅极结构

    公开(公告)号：US06664160B2

    公开(公告)日：2003-12-16

    申请号：US10298564

    申请日：2002-11-19

    申请人： Dae-Gyu Park ,  Heung-Jae Cho

    发明人： Dae-Gyu Park ,  Heung-Jae Cho

    IPC分类号： H01L2362

    CPC分类号： H01L29/517 ,  C23C16/405 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31604 ,  H01L29/66545

    摘要： A method for forming a gate structure beginning with a semiconductor substrate provided with an isolation region formed therein. An HfO2 layer and a conductive layer are formed on the semiconductor substrate, subsequently. The conductive layer and the HfO2 layer are patterned into the gate structure. By utilizing an HfO2 layer as a gate dielectric, an effective K of the gate dielectric can be controlled to within 18 to 25. In addition, by employing a CVD method for forming the HfO2 layer, it is possible to obtain a high K gate dielectric with excellent leakage current characteristic as well as a low interface state with both a gate electrode and a semiconductor substrate.

    摘要翻译： 一种形成栅极结构的方法，从形成有隔离区域的半导体衬底开始。 随后在半导体衬底上形成HfO 2层和导电层。 将导电层和HfO 2层图案化成栅极结构。 通过使用HfO 2层作为栅极电介质，可以将栅极电介质的有效K控制在18〜25的范围内。此外，通过采用CVD法形成HfO 2层，可以获得高K栅极电介质 具有优异的漏电流特性以及与栅电极和半导体衬底两者的低接口状态。