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    METHOD OF FORMING AN ACTIVE AREA WITH FLOATING GATE NEGATIVE OFFSET PROFILE IN FG NAND MEMORY
    71.
    发明申请
    METHOD OF FORMING AN ACTIVE AREA WITH FLOATING GATE NEGATIVE OFFSET PROFILE IN FG NAND MEMORY 有权
    在FG NAND存储器中形成具有浮动栅极负偏移轮廓的活动区域的方法

    公开(公告)号：US20140367762A1

    公开(公告)日：2014-12-18

    申请号：US14472611

    申请日：2014-08-29

    申请人： SANDISK TECHNOLOGIES INC.

    发明人： Ming Tian ,  Jayavel Pachamuthu ,  Atsushi Suyama ,  James Kai ,  Raghuveer S. Makala ,  Yao-Sheng Lee ,  Johann Alsmeier ,  Henry Chien ,  Masanori Terahara ,  Hirofumi Watatani

    IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L29/66

    CPC分类号： H01L29/66825 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices.

    摘要翻译： 可以通过第一蚀刻工艺对叠层进行构图，以形成限定图案化材料堆叠的侧壁表面的开口。 掩模层可以非均匀地沉积在图案化材料堆叠的上部的侧壁上，同时不沉积在图案化材料堆叠的下部的侧壁上。 开口的下部的侧壁可以使用第二蚀刻工艺横向凹入，其可以包括各向同性蚀刻部件。 开口的上部的侧壁可以朝向开口向内突出，以在开口的下部的侧壁上形成伸出。 可以使用突出端形成有用的结构，例如浮动栅极器件中的负偏移轮廓或用于垂直存储器件的垂直对准的控制栅电极。

    Metal Layer Air Gap Formation
    72.
    发明申请
    Metal Layer Air Gap Formation 有权
    金属层气隙形成

    公开(公告)号：US20130214415A1

    公开(公告)日：2013-08-22

    申请号：US13768934

    申请日：2013-02-15

    申请人： SanDisk Technologies Inc.

    发明人： Jayavel Pachamuthu ,  Hiroyuki Kinoshita ,  Vinod R. Purayath ,  George Matamis

    IPC分类号： H01L23/498 ,  H01L21/768

    CPC分类号： H01L23/49866 ,  H01L21/7682 ,  H01L21/76871 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11548 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Air gaps are provided to reduce interference and resistance between metal bit lines in non-volatile memory structures. Metal vias can be formed that are electrically coupled with the drain region of an underlying device and extend vertically with respect to the substrate surface to provide contacts for bit lines that are elongated in a column direction above. The metal vias can be separated by a dielectric fill material. Layer stack columns extend in a column direction over the dielectric fill and metal vias. Each layer stack column includes a metal bit line over a nucleation line. Each metal via contacts one of the layer stack columns at its nucleation line. A low temperature dielectric liner extends along sidewalls of the layer stack columns. A non-conformal dielectric overlies the layer stack columns defining a plurality of air gaps between the layer stack columns.

    摘要翻译： 提供空气间隙以减少非易失性存储器结构中的金属位线之间的干扰和电阻。 可以形成金属通孔，其与下面的器件的漏极区域电耦合并且相对于衬底表面垂直地延伸，以提供在列方向上延伸的位线的触点。 金属通孔可以通过介电填充材料分离。 层堆叠列在介电填充物和金属过孔的列方向上延伸。 每层堆叠柱包括在成核线上的金属位线。 每个金属通孔在其成核线处接触层堆叠列之一。 低温电介质衬垫沿着层堆叠柱的侧壁延伸。 非共形电介质覆盖在层堆叠列之间限定多个气隙之间的层堆叠列。

    Three-dimensional memory devices having a shaped epitaxial channel portion
    73.
    发明授权
    Three-dimensional memory devices having a shaped epitaxial channel portion 有权

    公开(公告)号：US09842851B2

    公开(公告)日：2017-12-12

    申请号：US14927990

    申请日：2015-10-30

    申请人： SANDISK TECHNOLOGIES INC.

    发明人： Jayavel Pachamuthu ,  Tuan Pham

    IPC分类号： H01L27/11 ,  H01L29/78 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/311

    CPC分类号： H01L27/11582 ,  H01L21/30608 ,  H01L21/3065 ,  H01L27/1157

    摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion.

    Vertical memory device with bit line air gap
    78.
    发明授权
    Vertical memory device with bit line air gap 有权
    具有位线气隙的垂直存储器件

    公开(公告)号：US09515085B2

    公开(公告)日：2016-12-06

    申请号：US14498033

    申请日：2014-09-26

    申请人： SanDisk Technologies, Inc.

    发明人： Peter Rabkin ,  Jilin Xia ,  Jayavel Pachamuthu

    IPC分类号： H01L27/115 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528

    CPC分类号： H01L27/11582 ,  H01L21/02381 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure includes a three-dimensional semiconductor device including a plurality of unit device structures located over a substrate. Each of the unit device structures includes a semiconductor channel including at least a portion extending vertically along a direction perpendicular to a top surface of the substrate, and a drain region contacting a top end of the semiconductor channel. The structure also includes a combination of a plurality of contact pillars and a contiguous volume that laterally surrounds the plurality of contact pillars. The plurality of contact pillars is in contact with the drain regions, and the contiguous volume has a dielectric constant less than 3.9.

    摘要翻译： 一种结构包括三维半导体器件，其包括位于衬底上方的多个单元器件结构。 每个单元器件结构包括半导体沟道，该半导体沟道至少包括沿垂直于衬底的顶表面的方向垂直延伸的部分，以及与半导体沟道的顶端接触的漏极区。 该结构还包括多个接触柱和横向围绕多个接触柱的连续体积的组合。 多个接触柱与漏极区域接触，并且连续的体积具有小于3.9的介电常数。

    STRESS PATTERNS TO DETECT SHORTS IN THREE DIMENSIONAL NON-VOLATILE MEMORY
    79.
    发明申请
    STRESS PATTERNS TO DETECT SHORTS IN THREE DIMENSIONAL NON-VOLATILE MEMORY 有权
    在三维非易失性存储器中检测短路的应力模式

    公开(公告)号：US20160343454A1

    公开(公告)日：2016-11-24

    申请号：US14716794

    申请日：2015-05-19

    申请人： SANDISK TECHNOLOGIES INC.

    发明人： Jayavel Pachamuthu ,  Sagar Magia ,  Ankitkumar Babariya ,  Jagdish Sabde

    IPC分类号： G11C29/50 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04

    CPC分类号： G11C29/025 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/06 ,  G11C29/10 ,  G11C29/50008 ,  H01L27/11582

    摘要： A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation.

    摘要翻译： 非易失性存储系统包括三维结构，其包括垂直列的存储器单元和与垂直列通信的管理电路。管理电路将一个或多个应力电压模式应用于垂直列，其中不同的电压施加到每个垂直 对相邻垂直列的列的列进行短路测试。 在施加一个或多个应力电压图案之后，管理电路测试相邻垂直列中的短对。 在一个实施例中，测试可以包括对每个垂直列中的存储器单元进行编程，其中数据与应力电压的模式匹配，从存储器单元的读取以及确定数据读取是否与编程的数据匹配。 施加应力电压和测试可以在制造期间或在用户操作期间的现场测试中进行。

    Method Of Forming 3D Vertical NAND With III-V Channel
    80.
    发明申请
    Method Of Forming 3D Vertical NAND With III-V Channel 有权
    用III-V通道形成3D垂直NAND的方法

    公开(公告)号：US20160284724A1

    公开(公告)日：2016-09-29

    申请号：US14666687

    申请日：2015-03-24

    申请人： SanDisk Technologies Inc.

    发明人： Peter Rabkin ,  Jayavel Pachamuthu ,  Johann Alsmeier ,  Masaaki Higashitani

    IPC分类号： H01L27/115 ,  H01L27/06 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28

    CPC分类号： H01L27/11582 ,  H01L21/02178 ,  H01L21/02192 ,  H01L27/0605 ,  H01L29/201 ,  H01L29/7926

    摘要： Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.

    摘要翻译： 本文公开了具有III-V复合通道的垂直NAND串的3D存储器以及制造方法。 III-V族化合物具有至少一个III族元素和至少一个V族元素。 III-V化合物提供高电子迁移率晶体管电池。 注意，与硅相比，III-V材料可能具有高得多的电子迁移率。 因此，可以实现更高的电池电流和整体电池性能。 此外，由于更高的载波移动性和速度，存储器件可能具有更好的读写效率。 存储单元的隧道电介质可以具有与III-V NAND通道直接接触的Al 2 O 3膜。 NAND通道的漏极端可以是与金属区域直接接触的金属III-V合金。 源极侧选择晶体管的主体可以由III-V族化合物或晶体硅形成。