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    SEMICONDUCTOR DEVICE
    71.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200343251A1

    公开(公告)日：2020-10-29

    申请号：US16810902

    申请日：2020-03-06

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

    IPC: H01L27/115 ,  H01L29/786 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  G11C11/24 ,  H01L29/24

    Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

    STORAGE DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
    72.
    发明申请
    STORAGE DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20200342928A1

    公开(公告)日：2020-10-29

    申请号：US16962309

    申请日：2020-01-14

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Hitoshi KUNITAKE

    IPC: G11C11/408 ,  H01L27/108

    Abstract: A novel storage device and a novel semiconductor device are provided.In the storage device, a cell array including a plurality of memory cells is stacked above a control circuit, and the cell array operates separately in a plurality of blocks. Furthermore, a plurality of electrodes are included between the control circuit and the cell array. The electrode is provided for a corresponding block to overlap with the block, and a potential of the electrode can be changed for each block. The electrode has a function of aback gate of a transistor included in the memory cell, and a potential of the electrode is changed for each block, whereby the electrical characteristics of the transistor included in the memory cell can be changed. Moreover, the electrode can reduce noise caused in the control circuit.

    Semiconductor Device and Method for Driving Semiconductor Device
    75.
    发明申请
    Semiconductor Device and Method for Driving Semiconductor Device 审中-公开
    用于驱动半导体器件的半导体器件和方法

    公开(公告)号：US20160351572A1

    公开(公告)日：2016-12-01

    申请号：US15164133

    申请日：2016-05-25

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tomoaki ATSUMI ,  Junpei SUGAO

    IPC: H01L27/105 ,  G11C11/4094 ,  G11C11/4096 ,  H01L29/786 ,  H01L27/12

    CPC classification number: G11C11/4094 ,  G11C11/401 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/1104 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78675 ,  H01L29/7869 ,  H01L29/78696

    Abstract: The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.

    Abstract translation: 半导体器件包括第一存储器单元和其上的第二存储器单元。 第一存储单元包括第一和第二晶体管，以及第一电容器。 第二存储单元包括第三和第四晶体管，以及第二电容器。 第一晶体管的栅极电连接到第二晶体管和第一电容器的源极和漏极之一。 第三晶体管的栅极电连接到第四晶体管和第二电容器的源极和漏极之一。 第一晶体管的源极和漏极之一电连接到第三晶体管的源极和漏极之一。 第二和第四晶体管包括氧化物半导体。 第一和第三晶体管的沟道长度方向基本上垂直于第二和第四晶体管的沟道长度方向。

    TEST METHOD OF SEMICONDUCTOR DEVICE
    76.
    发明申请
    TEST METHOD OF SEMICONDUCTOR DEVICE 有权
    半导体器件的测试方法

    公开(公告)号：US20160293276A1

    公开(公告)日：2016-10-06

    申请号：US15082431

    申请日：2016-03-28

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Kazuaki OHSHIMA

    IPC: G11C29/50 ,  G11C11/22

    CPC classification number: G11C29/50004 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/50016 ,  H01L27/108

    Abstract: The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

    Abstract translation: 半导体器件包括位线，晶体管，保持节点和电容器。 晶体管具有对保留节点进行充电或放电的功能。 电容器具有保持保持节点的电位的功能。 大于写入电压和阈值电压之和的电压被施加到晶体管的栅极。 当晶体管导通时，第一电位以浮置状态的基准电位提供给位线。 小于写入电压和阈值电压之和的电压被施加到晶体管的栅极。 当晶体管导通时，第二电位以浮置状态的基准电位提供给位线。 利用第一和第二电位，晶体管的阈值电压被计算而不受寄生电容和电容器的存储电容的变化的影响。

    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
    77.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 有权
    半导体器件和电子器件

    公开(公告)号：US20150294693A1

    公开(公告)日：2015-10-15

    申请号：US14681570

    申请日：2015-04-08

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Takanori MATSUZAKI ,  Hiroki INOUE ,  Shuhei NAGATSUKA ,  Yuto YAKUBO

    IPC: G11C5/02 ,  H01L27/12 ,  G11C5/06 ,  H01L29/24

    CPC classification number: G11C5/025 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/24

    Abstract: Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.

    Abstract translation: 提供一种能够实现面积减小，功耗降低，高速运转的半导体装置。 半导体器件10具有堆叠包括存储电路的电路31和包括放大电路的电路32的结构。 利用这种结构，可以在半导体器件10的面积的增加被抑制的同时将存储电路和放大器电路安装在半导体器件10上。 因此，可以减小半导体器件10的面积。 此外，使用OS晶体管形成电路，从而可以形成具有低截止电流并且可以高速操作的存储电路和放大器电路。 因此，可以实现半导体器件10的功耗的降低和操作速度的提高。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    78.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
    半导体器件及制造半导体器件的方法

    公开(公告)号：US20140027882A1

    公开(公告)日：2014-01-30

    申请号：US14037778

    申请日：2013-09-26

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tomoaki ATSUMI ,  Hiroki INOUE

    IPC: H01L49/02

    CPC classification number: H01L21/02683 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1255 ,  H01L27/1285 ,  H01L27/1296 ,  H01L28/40

    Abstract: In a semiconductor device including a digital circuit portion and an analog circuit portion having a capacitor portion provided over a substrate, the capacitor portion is provided with a first wiring, a second wiring and a plurality of blocks each having a plurality of capacitor elements. Further, each the plurality of capacitor elements provided in each block has a semiconductor film having a first impurity region and a plurality of second impurity regions provided apart with the first impurity region interposed therebetween, and a conductive film provided over the first impurity region with an insulating film therebetween. A capacitor is formed from the first impurity region, the insulating film, and the conductive film.

    Abstract translation: 在包括数字电路部分和具有设置在衬底上的电容器部分的模拟电路部分的半导体器件中，电容器部分设置有第一布线，第二布线和多个具有多个电容器元件的块。 此外，设置在每个块中的多个电容器元件中的每一个具有半导体膜，该半导体膜具有第一杂质区和设置有分隔开第一杂质区的多个第二杂质区，并且在第一杂质区上设置有导电膜， 绝缘膜。 由第一杂质区，绝缘膜和导电膜形成电容器。

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