公开(公告)号：US20150019836A1

公开(公告)日：2015-01-15

申请号：US14327066

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mel Alan Phipps ,  Todd T. Hahn ,  Joseph Zbiciak

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/3012

Abstract: The number of registers required is reduced by overlapping scalar and vector registers. This also allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are minimized by restricting read access. Dedicated predicate registers reduces requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.

Abstract translation: 所需的寄存器数量通过重叠标量和向量寄存器来减少。 这也允许在混合标量和向量指令时增加编译器的灵活性。 通过限制读取访问来使本地寄存器读取端口最小化。 专用谓词寄存器减少通用寄存器的要求，并允许通过允许将谓词寄存器放置在谓词单元旁边来减少关键定时路径。

公开(公告)号：US20250103510A1

公开(公告)日：2025-03-27

申请号：US18973226

申请日：2024-12-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

Abstract: In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.

公开(公告)号：US12124728B2

公开(公告)日：2024-10-22

申请号：US18353181

申请日：2023-07-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Soujanya Narnur

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/80

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1668 ,  G06F15/8076

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

公开(公告)号：US12072812B2

公开(公告)日：2024-08-27

申请号：US17237391

申请日：2021-04-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/30 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1045 ,  G06F17/16 ,  H03H17/06 ,  G06F15/78

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.

公开(公告)号：US20240063827A1

公开(公告)日：2024-02-22

申请号：US18498196

申请日：2023-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dheera Balasubramanian ,  Joseph Zbiciak ,  Duc Quang Bui ,  Timothy David Anderson

IPC: H03M13/00 ,  G06F9/38 ,  H03M13/27

CPC classification number: H03M13/6561 ,  G06F9/38 ,  H03M13/2789 ,  H03M13/276

Abstract: A system, method, and device are shown that are operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network by selectably switching bit positions of the input data stream. In some examples, a device includes a first circuit configured to selectably switch bit positions of a first subset of the data stream with a second subset of the data stream and a second circuit configured to: selectably switch bit positions of a first subset of the first subset of the data stream with a second subset of the first subset of the data stream, and selectably switch bit positions of a first subset of the second subset of the data stream with a second subset of the second subset of the data stream.

公开(公告)号：US20230418605A1

公开(公告)日：2023-12-28

申请号：US18243326

申请日：2023-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Peter Richard Dent

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/30043

Abstract: Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.

公开(公告)号：US11804858B2

公开(公告)日：2023-10-31

申请号：US17378886

申请日：2021-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dheera Balasubramanian ,  Joseph Zbiciak ,  Duc Quang Bui ,  Timothy David Anderson

IPC: H03M13/00 ,  H03M13/27 ,  G06F9/38

CPC classification number: H03M13/6561 ,  G06F9/38 ,  H03M13/2789 ,  H03M13/276

Abstract: A system, method, and device is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network that includes a plurality of layers of multiplexers. Many transformations are possible with such a network which may include separate control of each multiplexer.

公开(公告)号：US20230325189A1

公开(公告)日：2023-10-12

申请号：US18208444

申请日：2023-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30167 ,  G06F9/3853 ,  G06F7/49994 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/3822

Abstract: In a very long instruction word (VLIW) central processing unit instructions are grouped into execute packets that execute in parallel. A constant may be specified or extended by bits in a constant extension instruction in the same execute packet. If an instruction includes an indication of constant extension, the decoder employs bits of a constant extension instruction to extend the constant of an immediate field. Two or more constant extension slots are permitted in each execute packet, each extending constants for a different predetermined subset of functional unit instructions. In an alternative embodiment, more than one functional unit may have constants extended from the same constant extension instruction employing the same extended bits. A long extended constant may be formed using the extension bits of two constant extension instructions.

公开(公告)号：US11704046B2

公开(公告)日：2023-07-18

申请号：US17722477

申请日：2022-04-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Soujanya Narnur

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/80

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1668 ,  G06F15/8076

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

公开(公告)号：US11681532B2

公开(公告)日：2023-06-20

申请号：US16846686

申请日：2020-04-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/499 ,  G06F15/80

CPC classification number: G06F9/30167 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/3822 ,  G06F9/3853 ,  G06F7/49994 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3836 ,  G06F15/8053

Abstract: In a very long instruction word (VLIW) central processing unit instructions are grouped into execute packets that execute in parallel. A constant may be specified or extended by bits in a constant extension instruction in the same execute packet. If an instruction includes an indication of constant extension, the decoder employs bits of a constant extension instruction to extend the constant of an immediate field. Two or more constant extension slots are permitted in each execute packet, each extending constants for a different predetermined subset of functional unit instructions. In an alternative embodiment, more than one functional unit may have constants extended from the same constant extension instruction employing the same extended bits. A long extended constant may be formed using the extension bits of two constant extension instructions.