公开(公告)号：US20180166274A1

公开(公告)日：2018-06-14

申请号：US15375266

申请日：2016-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Huei Lin ,  Yen-Yu Chen ,  Chih-Pin Tsao ,  Shih-Hsun Chang

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/02326 ,  H01L21/76888 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

Abstract: An NMOS transistor gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region and lining an inner sidewall of the spacer, a bottom barrier layer conformally disposed on the gate dielectric layer, a work function metal layer disposed on the bottom barrier layer, and a filling metal partially wrapped by the work function metal layer. The bottom barrier layer has an oxygen concentration higher than a nitrogen concentration. The bottom barrier layer is in direct contact with the gate dielectric layer. The bottom barrier layer includes a material selected from Ta, TaN, TaTi, TaTiN and a combination thereof.

公开(公告)号：US12218181B2

公开(公告)日：2025-02-04

申请号：US16830981

申请日：2020-03-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Anhao Cheng ,  Fang-Ting Kuo ,  Yen-Yu Chen

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02

Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect layer disposed on a substrate, where the first electrode bilayer includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the dielectric layer where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

公开(公告)号：US12199033B2

公开(公告)日：2025-01-14

申请号：US18180079

申请日：2023-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung Hsun Lin ,  Wei-Chun Hua ,  Wen-Chu Huang ,  Yen-Yu Chen ,  Che-Chih Hsu ,  Chinyu Su ,  Wen Han Hung

IPC: H01L23/52 ,  H01L21/027 ,  H01L21/768 ,  H01L23/522 ,  H01L23/64 ,  H01L23/66 ,  H01L49/02

Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.

公开(公告)号：US20240371691A1

公开(公告)日：2024-11-07

申请号：US18774289

申请日：2024-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

IPC: H01L21/768 ,  H01L21/225 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

Abstract: A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

公开(公告)号：US12094698B2

公开(公告)日：2024-09-17

申请号：US18317009

申请日：2023-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsi Wang ,  Kun-Che Ho ,  Yen-Yu Chen

IPC: H01J37/34 ,  C23C14/34 ,  C23C14/35 ,  H01L21/02

CPC classification number: H01J37/3455 ,  C23C14/3407 ,  C23C14/3442 ,  C23C14/351 ,  H01J37/3405 ,  H01J37/3414 ,  H01J37/3435 ,  H01J37/3452 ,  H01J37/3461 ,  H01L21/02631

Abstract: A method includes loading a wafer into a sputtering chamber, followed by depositing a film over the wafer by performing a sputtering process in the sputtering chamber. In the sputtering process, a target is bombarded by ions that are applied with a magnetic field using a magnetron. The magnetron includes a magnetic element over the target, an arm assembly connected to the magnetic element, a hinge mechanism connecting the arm assembly and a rotational shaft. The arm assembly includes a first prong and a second prong at opposite sides of the hinge mechanism. The magnetron further includes a controller that controls motion of the first arm assembly, enabling the first prong to revolve in an orbital motion path about the first hinge mechanism while the second prong remains stationary.

公开(公告)号：US12054823B2

公开(公告)日：2024-08-06

申请号：US17190761

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Lee ,  Yen-Yu Chen

IPC: H01L29/40 ,  C23C14/02 ,  C23C14/14 ,  C23C14/56 ,  C23C14/58 ,  C23C16/02 ,  C23C16/06 ,  C23C16/56 ,  H01J37/32 ,  H01L21/02

CPC classification number: C23C16/0245 ,  C23C14/021 ,  C23C14/14 ,  C23C14/566 ,  C23C14/5873 ,  C23C16/06 ,  C23C16/56 ,  H01J37/32743 ,  H01J37/32788 ,  H01J37/32899 ,  H01L21/0206 ,  H01L21/02068 ,  H01L29/401 ,  H01J37/321 ,  H01J37/32357 ,  H01J2237/335

Abstract: Semiconductor processing apparatuses and methods are provided in which a pre-clean chamber receives a semiconductor wafer from a metal gate layer deposition chamber and at least partially removes an oxide layer on a metal gate layer. In some embodiments, a semiconductor processing apparatus includes a plurality of metal gate layer deposition chambers. Each of the metal gate layer deposition chambers is configured to form a metal gate layer on a semiconductor wafer. At least one pre-clean chamber of the apparatus is configured to receive the semiconductor wafer from one of the metal gate layer deposition chamber and at least partially remove an oxide layer on the metal gate layer.

公开(公告)号：US11823908B2

公开(公告)日：2023-11-21

申请号：US17549673

申请日：2021-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Yu Chen ,  Yu-Chi Lu ,  Chih-Pin Tsao ,  Shih-Hsun Chang

IPC: H01L21/28 ,  H01L29/49

CPC classification number: H01L21/28088 ,  H01L21/28185 ,  H01L29/4966

Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.

公开(公告)号：US11502050B2

公开(公告)日：2022-11-15

申请号：US17170624

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L21/02 ,  H01L23/532 ,  H01L23/525 ,  H01L23/00

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US11437420B2

公开(公告)日：2022-09-06

申请号：US16733433

申请日：2020-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Chi Hung ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wei Chuang Wu ,  Yen-Yu Chen ,  Chih-Kuan Yu

IPC: H01L27/146

Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

公开(公告)号：US20220081759A1

公开(公告)日：2022-03-17

申请号：US17190761

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Lee ,  Yen-Yu Chen

IPC: C23C16/02 ,  H01L29/40 ,  H01L21/02 ,  H01J37/32 ,  C23C14/02 ,  C23C14/14 ,  C23C14/56 ,  C23C14/58 ,  C23C16/06 ,  C23C16/56

Abstract: Semiconductor processing apparatuses and methods are provided in which a pre-clean chamber receives a semiconductor wafer from a metal gate layer deposition chamber and at least partially removes an oxide layer on a metal gate layer. In some embodiments, a semiconductor processing apparatus includes a plurality of metal gate layer deposition chambers. Each of the metal gate layer deposition chambers is configured to form a metal gate layer on a semiconductor wafer. At least one pre-clean chamber of the apparatus is configured to receive the semiconductor wafer from one of the metal gate layer deposition chamber and at least partially remove an oxide layer on the metal gate layer.