公开(公告)号：US20190252394A1

公开(公告)日：2019-08-15

申请号：US16396963

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/1157 ,  H01L27/11568 ,  H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US10381358B2

公开(公告)日：2019-08-13

申请号：US15987089

申请日：2018-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/11524 ,  H01L27/11548 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L29/788 ,  H01L27/11534 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11529

Abstract: In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area. The mask layer in the memory cell area is patterned by using the resist mask as an etching mask. The substrate is etched in the memory cell area. After etching the substrate, a memory cell structure in the memory cell area and a gate structure for the logic circuit are formed. A dielectric layer is formed to cover the memory cell structure and the gate structure. A planarization operation is performed on the dielectric layer. An upper portion of the memory cell structure is planarized during the planarization operation.

公开(公告)号：US10347649B2

公开(公告)日：2019-07-09

申请号：US15938043

申请日：2018-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L29/792 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11568

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US10276588B2

公开(公告)日：2019-04-30

申请号：US15582889

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Ya-Chen Kao ,  Yi Hsien Lu

IPC: H01L21/336 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

公开(公告)号：US20190019567A1

公开(公告)日：2019-01-17

申请号：US16122104

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Wei Cheng Wu ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: G11C29/02 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  G01R31/28 ,  H01L27/11568 ,  H01L29/51 ,  H01L23/544 ,  H01L29/49 ,  G11C29/56 ,  H01L21/66 ,  H01L27/11526 ,  H01L27/11573

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.

公开(公告)号：US09983257B2

公开(公告)日：2018-05-29

申请号：US14883791

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: H01L21/768 ,  G01R31/26 ,  H01L23/544 ,  H01L23/528 ,  H01L29/51 ,  H01L29/49 ,  H01L27/11568 ,  H01L29/423 ,  H01L21/3213 ,  H01L27/11573 ,  H01L21/66

CPC classification number: G01R31/2644 ,  H01L21/32133 ,  H01L21/76877 ,  H01L22/34 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/00 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L2223/54406 ,  H01L2223/54453 ,  H01L2223/5446

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.

公开(公告)号：US09960176B2

公开(公告)日：2018-05-01

申请号：US14933046

申请日：2015-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L21/8238 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11568

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US20170345841A1

公开(公告)日：2017-11-30

申请号：US15167070

申请日：2016-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Chien-Hung Chang

IPC: H01L27/11573 ,  H01L21/28 ,  H01L29/51 ,  H01L21/311 ,  H01L29/423 ,  H01L27/11568 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L27/11573 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11536 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region. A sacrificial logic gate electrode is formed within the logic region together with a control gate electrode or a select gate electrode within the memory region by patterning a control gate layer or a select gate layer. A first inter-layer dielectric layer is formed between the sacrificial logic gate electrode and the control gate electrode or the select gate electrode. A hard mask is formed over the first inter-layer dielectric layer to cover the memory region and to expose the sacrificial logic gate electrode within the logic region. The sacrificial logic gate electrode is replaced with a high-k gate dielectric layer and a metal layer to form a metal gate electrode within the logic region.

公开(公告)号：US20170110201A1

公开(公告)日：2017-04-20

申请号：US14883787

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Wei Cheng Wu ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: G11C29/02 ,  H01L29/423 ,  H01L23/528 ,  H01L23/544 ,  G01R31/28 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L21/3213 ,  H01L27/115 ,  H01L29/51

CPC classification number: G11C29/025 ,  G01R31/2884 ,  G11C2029/5602 ,  H01L21/28282 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76877 ,  H01L22/34 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L2223/54406 ,  H01L2223/54453 ,  H01L2223/5446

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character.

公开(公告)号：US09583591B2

公开(公告)日：2017-02-28

申请号：US14210796

申请日：2014-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chin-Yi Huang ,  Shih-Chang Liu ,  Chang-Ming Wu

IPC: H01L21/77 ,  H01L21/336 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L27/11534 ,  H01L27/11521 ,  H01L29/66545

Abstract: The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary.

Abstract translation: 本公开涉及一种在采用替代门技术的HKMG集成电路中嵌入ESF3存储器的方法。 ESF3存储器形成在凹陷的衬底上，防止在ILD层执行的CMP工艺期间对存储器控制栅极的损坏。 在存储单元和外围电路边界之间的过渡区域中也形成非对称隔离区。