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    High Speed Semiconductor Devices
    72.
    发明申请
    High Speed Semiconductor Devices 审中-公开

    公开(公告)号：US20200161439A1

    公开(公告)日：2020-05-21

    申请号：US16406154

    申请日：2019-05-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.

    3D semiconductor package including memory array
    77.
    发明授权
    3D semiconductor package including memory array 有权

    公开(公告)号：US12293999B2

    公开(公告)日：2025-05-06

    申请号：US17814194

    申请日：2022-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Yu-Ming Lin

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/18 ,  H01L29/24 ,  H10B51/20 ,  H10B51/30

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

    Memory array contact structures
    79.
    发明授权
    Memory array contact structures 有权

    公开(公告)号：US12225731B2

    公开(公告)日：2025-02-11

    申请号：US17818638

    申请日：2022-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Yu Chang ,  Meng-Han Lin ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

    IPC: H10B51/20 ,  G11C11/22 ,  H01L23/535 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

    Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

    Method and device for forming metal gate electrodes for transistors
    80.
    发明授权
    Method and device for forming metal gate electrodes for transistors 有权

    公开(公告)号：US12205819B2

    公开(公告)日：2025-01-21

    申请号：US18061794

    申请日：2022-12-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huan-Chieh Su ,  Zhi-Chang Lin ,  Ting-Hung Hsu ,  Jia-Ni Yu ,  Wei-Hao Wu ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L29/66 ,  H01L21/28 ,  H01L21/308 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51 ,  H01L29/78

    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

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