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公开(公告)号:US10685884B2
公开(公告)日:2020-06-16
申请号:US15665230
申请日:2017-07-31
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Yasutoshi Okuno , Cheng-Yi Peng , Ziwei Fang , I-Ming Chang , Akira Mineji , Yu-Ming Lin , Meng-Hsuan Hsiao
IPC: H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/203 , H01L27/092 , H01L21/8238 , H01L29/165 , H01L27/12 , H01L21/84 , H01L29/161
Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01≤x≤0.1.
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公开(公告)号:US20200161439A1
公开(公告)日:2020-05-21
申请号:US16406154
申请日:2019-05-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jia-Chuan You , Chia-Hao Chang , Tien-Lu Lin , Yu-Ming Lin , Chih-Hao Wang
IPC: H01L29/417 , H01L29/66 , H01L29/78
Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.
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公开(公告)号:US20200098622A1
公开(公告)日:2020-03-26
申请号:US16510554
申请日:2019-07-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Huan-Chieh Su , Chih-Hao Wang , Kuo-Cheng Chiang , Wei-Hao Wu , Zhi-Chang Lin , Jia-Ni Yu , Yu-Ming Lin , Chung-Wei Hsu
IPC: H01L21/768 , H01L21/8238 , H01L27/092 , H01L29/66 , H01L29/78
Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
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公开(公告)号:US10157790B1
公开(公告)日:2018-12-18
申请号:US15907148
申请日:2018-02-27
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jia-Chuan You , Chia-Hao Chang , Wei-Hao Wu , Yu-Ming Lin , Chih-Hao Wang
IPC: H01L21/768 , H01L29/66 , H01L21/28 , H01L21/311 , H01L23/522 , H01L21/033
Abstract: A semiconductor device includes a substrate, a conductive feature, a conductive cap, a dielectric mask, a gate spacer, and a gate stack. The substrate has a source/drain region. The conductive feature is on the source/drain region. The conductive cap is on the conductive feature. The dielectric mask is on the conductive cap and is spaced apart from the conductive feature by the conductive cap. The gate spacer is on the substrate, in which a top surface of the gate spacer is level with a top surface of the mask. The gate stack abuts the gate spacer.
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公开(公告)号:US10134915B2
公开(公告)日:2018-11-20
申请号:US15615498
申请日:2017-06-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jean-Pierre Colinge , Chung-Cheng Wu , Carlos H. Diaz , Chih-Hao Wang , Ken-Ichi Goto , Ta-Pen Guo , Yee-Chia Yeo , Zhiqiang Wu , Yu-Ming Lin
IPC: H01L21/02 , H01L29/786 , H01L27/088 , H01L29/16 , H01L29/24 , H01L21/8256 , H01L21/8238 , H01L29/78
Abstract: Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.
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公开(公告)号:US10084066B2
公开(公告)日:2018-09-25
申请号:US15429335
申请日:2017-02-10
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Yu-Ming Lin , Ken-Ichi Goto
IPC: H01L21/84 , H01L29/66 , H01L21/768 , H01L21/02 , H01L29/78 , H01L23/535 , H01L29/10 , H01L29/24 , H01L29/16
CPC classification number: H01L29/66795 , H01L21/02167 , H01L21/0217 , H01L21/02266 , H01L21/02271 , H01L21/0228 , H01L21/02381 , H01L21/02422 , H01L21/02521 , H01L21/02527 , H01L21/02568 , H01L21/0262 , H01L21/76805 , H01L21/76895 , H01L21/76897 , H01L23/535 , H01L29/1037 , H01L29/1606 , H01L29/24 , H01L29/41791 , H01L29/66545 , H01L29/785
Abstract: A semiconductor device including a Fin FET device includes a fin structure protruding from a substrate layer and having a length extending in a first direction. A channel layer is formed on the fin structure. A gate stack including a gate electrode layer and a gate dielectric layer extending in a second direction perpendicular to the first direction is formed over the channel layer covering a portion of the length of the fin structure. The source and drain contacts are formed over trenches that extend into a portion of a height of the fin structure.
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公开(公告)号:US12293999B2
公开(公告)日:2025-05-06
申请号:US17814194
申请日:2022-07-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Bo-Feng Young , Sai-Hooi Yeong , Han-Jong Chia , Sheng-Chen Wang , Yu-Ming Lin
Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.
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公开(公告)号:US12243781B2
公开(公告)日:2025-03-04
申请号:US17874267
申请日:2022-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Cheng-Chi Chuang , Li-Zhen Yu , Yi-Hsun Chiu , Yu-Ming Lin , Chih-Hao Wang
IPC: H01L21/8234 , H01L21/768 , H01L29/66 , H01L29/78
Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.
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公开(公告)号:US12225731B2
公开(公告)日:2025-02-11
申请号:US17818638
申请日:2022-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Yu Chang , Meng-Han Lin , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin
Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.
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公开(公告)号:US12205819B2
公开(公告)日:2025-01-21
申请号:US18061794
申请日:2022-12-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Huan-Chieh Su , Zhi-Chang Lin , Ting-Hung Hsu , Jia-Ni Yu , Wei-Hao Wu , Yu-Ming Lin , Chih-Hao Wang
IPC: H01L29/66 , H01L21/28 , H01L21/308 , H01L21/8238 , H01L27/092 , H01L29/51 , H01L29/78
Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.
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