公开(公告)号：US20170194424A1

公开(公告)日：2017-07-06

申请号：US15290772

申请日：2016-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Chun Huang ,  Bor Chiuan Hsieh ,  Pei-Ren Jeng ,  Tai-Chun Huang ,  Tze-Liang Lee

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/0649 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/324 ,  H01L21/76227 ,  H01L29/66795

Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

公开(公告)号：US09691898B2

公开(公告)日：2017-06-27

申请号：US14134302

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Chang Sung ,  Tsz-Mei Kwok ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li

IPC: C30B25/14 ,  H01L29/36 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/324 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

Abstract: The present disclosure relates to a transistor device having a strained source/drain region comprising a strained inducing material having a discontinuous germanium concentration profile. In some embodiments, the transistor device has a gate structure disposed onto a semiconductor substrate. A source/drain region having a strain inducing material is disposed along a side of the gate structure within a source/drain recess in the semiconductor substrate. The strain inducing material has a discontinuous germanium concentration profile along a line extending from a bottom surface of the source/drain recess to a top surface of the source/drain recess. The discontinuous germanium concentration profile provides improved strain boosting and dislocation propagation.

公开(公告)号：US09228260B1

公开(公告)日：2016-01-05

申请号：US14447403

申请日：2014-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsai-Fu Hsiao ,  Chun-Yao Wang ,  Tai-Chun Huang ,  Tze-Liang Lee

IPC: H01L21/26 ,  H01L21/42 ,  C23C16/44 ,  C23C16/455 ,  H01L21/67

CPC classification number: H01L21/67109

Abstract: A wafer processing chamber is provided, including a first processing gas supply unit and a second processing gas supply unit. The first processing gas supply unit is configured for supplying a first processing gas to form a first processing zone in the wafer processing chamber. The second processing gas supply unit is configured for supplying a second processing gas into the wafer processing chamber to form a second processing zone in the wafer processing chamber. In the wafer processing chamber, the first processing zone and the second processing zone are virtually separated from each other, such that a process wafer in the first processing zone may be performed a different process from another process wafer in the second processing zone at the same time. Further, a heat treatment apparatus and a method for processing wafers also provide herein.

Abstract translation: 提供了晶片处理室，包括第一处理气体供应单元和第二处理气体供应单元。 第一处理气体供给单元被配置为提供第一处理气体以在晶片处理室中形成第一处理区域。 第二处理气体供给单元被配置为将第二处理气体供应到晶片处理室中，以在晶片处理室中形成第二处理区域。 在晶片处理室中，第一处理区域和第二处理区域实际上彼此分离，使得第一处理区域中的处理晶片可以在相同的第二处理区域中与另一处理晶片进行不同的处理 时间。 此外，本文还提供了热处理装置和处理晶片的方法。

公开(公告)号：US20150179796A1

公开(公告)日：2015-06-25

申请号：US14134302

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Chang Sung ,  Tsz-Mei Kwok ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/324 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

Abstract: The present disclosure relates to a transistor device having a strained source/drain region comprising a strained inducing material having a discontinuous germanium concentration profile. In some embodiments, the transistor device has a gate structure disposed onto a semiconductor substrate. A source/drain region having a strain inducing material is disposed along a side of the gate structure within a source/drain recess in the semiconductor substrate. The strain inducing material has a discontinuous germanium concentration profile along a line extending from a bottom surface of the source/drain recess to a top surface of the source/drain recess. The discontinuous germanium concentration profile provides improved strain boosting and dislocation propagation.

Abstract translation: 本发明涉及具有应变源极/漏极区域的晶体管器件，其包括具有不连续锗浓度分布的应变诱发材料。 在一些实施例中，晶体管器件具有设置在半导体衬底上的栅极结构。 具有应变诱导材料的源极/漏极区域沿着栅极结构的侧面设置在半导体衬底中的源极/漏极凹部内。 应变诱导材料沿着从源极/漏极凹部的底表面延伸到源极/漏极凹部的顶表面的线具有不连续的锗浓度分布。 不连续的锗浓度分布提供改进的应变增强和位错传播。

公开(公告)号：US12261036B2

公开(公告)日：2025-03-25

申请号：US18358508

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Che Hsieh ,  Ching Yu Huang ,  Hsin-Hao Yeh ,  Chunyao Wang ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

公开(公告)号：US12237419B2

公开(公告)日：2025-02-25

申请号：US17668143

申请日：2022-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chi-Hao Chang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a first source/drain region and a second source/drain region in a semiconductor fin; depositing a first dielectric layer over the first source/drain region and the second source/drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.

公开(公告)号：US12183577B2

公开(公告)日：2024-12-31

申请号：US17332553

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Kai Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.

公开(公告)号：US20240429313A1

公开(公告)日：2024-12-26

申请号：US18476619

申请日：2023-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Cheng Shiau ,  Chung-Ting Ko ,  Ting-Hsiang Chang ,  Shu Ling Liao ,  Sung-En Lin ,  Tai-Chun Huang ,  Tze-Liang Lee

IPC: H01L29/775 ,  H01L21/02 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A method includes etching a semiconductor region aside of a gate stack to form a recess, forming a dielectric layer at a bottom of the recess, selectively forming a first semiconductor layer at the bottom of the recess, and epitaxially growing a second semiconductor layer on the first semiconductor layer. A bottom surface of the first semiconductor layer forms an interface with a top surface of the dielectric layer, with the interface extending to opposing sides of the recess. The selectively forming the first semiconductor layer comprises a first deposition process performed under first process conditions. The second semiconductor layer is formed using a second deposition process under second process conditions. The second process conditions are different from the first process conditions.

公开(公告)号：US12154973B2

公开(公告)日：2024-11-26

申请号：US17592995

申请日：2022-02-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Jung Ho ,  Tze-Liang Lee

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a recess between gate spacers of the gate structure by recessing the gate structure below upper surfaces of the gate spacers; depositing a first layer of a dielectric material in the recess along sidewalls and a bottom of the recess; after depositing the first layer, performing a first etching process to remove portions of the first layer of the dielectric material; and after the first etching process, depositing a second layer of the dielectric material in the recess over the first layer of the dielectric material.

公开(公告)号：US20240387179A1

公开(公告)日：2024-11-21

申请号：US18785509

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Tze-Liang Lee

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.