公开(公告)号：US20090231921A1

公开(公告)日：2009-09-17

申请号：US12389361

申请日：2009-02-19

申请人： Shinichiro Kimura ,  Yasuhiro Shimamoto ,  Digh Hisamoto

发明人： Shinichiro Kimura ,  Yasuhiro Shimamoto ,  Digh Hisamoto

IPC分类号： G11C16/06 ,  H01L21/336 ,  H01L29/792 ,  G11C5/14

CPC分类号： H01L27/11568 ,  H01L29/42328 ,  H01L29/792

摘要： In a nonvolatile semiconductor storage device having a split-gate memory cell including a control gate electrode and a sidewall memory gate electrode and a single-gate memory cell including a single memory gate electrode on the same silicon substrate, the control gate electrode is formed in a first region via a control gate insulating film, the sidewall memory gate electrode is formed in the first region via a charge trapping film, and at the same time, a single memory gate electrode is formed in a second region via the charge trapping film. At this time, the sidewall memory gate electrode and the single memory gate electrode are formed in the same process, and the control gate electrode and the sidewall memory gate electrode are formed so as to be adjacently disposed to each other in a state of being electrically isolated from each other.

摘要翻译： 在具有包括控制栅电极和侧壁存储栅电极的分闸存储单元的非易失性半导体存储器件和在同一硅衬底上包括单个存储栅电极的单栅极存储单元中，形成控制栅电极 经由控制栅极绝缘膜的第一区域，所述侧壁存储栅电极经由电荷捕获膜形成在所述第一区域中，并且同时经由电荷捕获膜在第二区域中形成单个存储器栅电极。 此时，侧壁存储器栅极电极和单个存储器栅极电极以相同的工艺形成，并且控制栅极电极和侧壁存储栅电极形成为在电气的状态下彼此相邻地设置 彼此隔离

公开(公告)号：US09209171B2

公开(公告)日：2015-12-08

申请号：US13812181

申请日：2011-06-20

申请人： Digh Hisamoto ,  Shinichi Saito ,  Akio Shima ,  Hiroyuki Yoshimoto

发明人： Digh Hisamoto ,  Shinichi Saito ,  Akio Shima ,  Hiroyuki Yoshimoto

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/07 ,  H01L27/092 ,  H01L27/11 ,  H01L27/115 ,  H01L27/12 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04 ,  H01L27/102 ,  G11C11/412

CPC分类号： H01L27/1203 ,  G11C11/412 ,  G11C16/0408 ,  H01L21/8249 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0623 ,  H01L27/0705 ,  H01L27/092 ,  H01L27/1025 ,  H01L27/1026 ,  H01L27/11 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/1004 ,  H01L29/1033 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7311 ,  H01L29/788 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage.

摘要翻译： 提供了与MOSFET相比具有与常规MOSFET相同的可集成性的半导体元件，即在室温下S值小于60mV /阶的优异的开关特性。 组合MOSFET和具有隧道结的隧道双极晶体管配置了一个半导体元件，其相对于栅极电压的变化（S值小于60mV /次）显示出漏极电流的突然变化，即使在 低电压。

公开(公告)号：US08319274B2

公开(公告)日：2012-11-27

申请号：US11829248

申请日：2007-07-27

申请人： Digh Hisamoto ,  Itaru Yanagi ,  Yasuhiro Shimamoto ,  Toshiyuki Mine ,  Yutaka Okuyama

发明人： Digh Hisamoto ,  Itaru Yanagi ,  Yasuhiro Shimamoto ,  Toshiyuki Mine ,  Yutaka Okuyama

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0425 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

摘要： A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of a silicon nitride film containing oxygen, and a fourth insulator formed of a silicon oxide film in this order on a main surface of a semiconductor substrate. Holes are injected into the charge-trapping layer from a gate electrode side. Accordingly, since the operations can be achieved without the penetration of the holes through the interface in contact to the channel and the first insulator, the deterioration in rewriting endurance and the charge-trapping characteristics due to the deterioration of the first insulator does not occur, and highly efficient rewriting (writing and erasing) characteristics and stable charge-trapping characteristics can be achieved.

摘要翻译： 作为具有绝缘体栅极场效应晶体管的结构的非易失性存储单元的电荷捕获层的栅极介质通过层叠由氧化硅膜形成的第一绝缘体，由氮化硅膜形成的第二绝缘体 由半导体衬底的主表面依次由含有氧的氮化硅膜构成的第三绝缘体和由氧化硅膜形成的第四绝缘体构成。 孔从栅电极侧注入电荷捕获层。 因此，由于可以在没有孔穿过与沟道和第一绝缘体接触的界面的情况下实现操作，所以不会发生由于第一绝缘体的劣化导致的重写耐久性和电荷捕获特性的劣化， 并且可以实现高效的重写（写入和擦除）特性和稳定的电荷捕获特性。

公开(公告)号：US20110242888A1

公开(公告)日：2011-10-06

申请号：US13075169

申请日：2011-03-29

申请人： Tsuyoshi ARIGANE ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Yutaka Okuyama

发明人： Tsuyoshi ARIGANE ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Yutaka Okuyama

IPC分类号： G11C11/34 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/792

摘要： The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap.

摘要翻译： 半导体器件包括在半导体衬底的主表面中的非易失性存储单元。 非易失性存储单元在半导体衬底上具有第一绝缘膜，导电膜，第二绝缘膜，能够存储电荷的电荷存储膜，电荷存储膜上的第三绝缘膜，第一栅电极，第四绝缘膜 绝缘膜与从第一绝缘膜到前述第一栅电极的层叠膜接触;第五绝缘膜，与上述半导体衬底上的第一绝缘膜并置，形成在第五绝缘膜上的第二栅电极， 与第四绝缘膜的侧表面上的上述第一栅电极相邻，以及其间插入第一和第二栅电极的源/漏区。 导电膜和电荷存储膜形成为二维重叠。

公开(公告)号：US20100261327A1

公开(公告)日：2010-10-14

申请号：US12822157

申请日：2010-06-23

申请人： TSUYOSHI ARIGANE ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

发明人： TSUYOSHI ARIGANE ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

IPC分类号： H01L21/336

CPC分类号： H01L29/42328 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7883

摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).

摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。

公开(公告)号：US07812398B2

公开(公告)日：2010-10-12

申请号：US12400324

申请日：2009-03-09

申请人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

发明人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

IPC分类号： H01L27/01 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/7846 ,  H01L29/785

摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，增加了pMOSFET的驱动电流。 在（100）硅衬底上形成具有<100>方向的沟道的pMOSFET。 通过STI在垂直于通道的方向上施加压应力。

公开(公告)号：US07759720B2

公开(公告)日：2010-07-20

申请号：US12273308

申请日：2008-11-18

申请人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

发明人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

IPC分类号： H01L29/94

CPC分类号： H01L29/42328 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7883

摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).

摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。

公开(公告)号：US07687845B2

公开(公告)日：2010-03-30

申请号：US11943909

申请日：2007-11-21

申请人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto

发明人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto

IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  G11C16/0466 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7851

摘要： A charge trapping layer in an element isolation region and that in an isolation region between a memory transistor and a selection transistor are removed so that the charges are not injected or trapped in the regions. Also, in an element isolation region, gate electrodes of each memory transistor are united at a position higher than a gate electrode of the selection transistor from a surface of a silicon substrate in an element isolation region, thereby reducing the capacitance between the memory transistor and the selection transistor.

摘要翻译： 去除元件隔离区域中的电荷捕获层，以及在存储晶体管和选择晶体管之间的隔离区域中的电荷捕获层，使得电荷不被注入或被捕获在该区域中。 此外，在元件隔离区域中，每个存储晶体管的栅极电极从元件隔离区域中的硅衬底的表面在选择晶体管的栅电极的高位置处结合，从而减小存储晶体管和 选择晶体管。

公开(公告)号：US20090132974A1

公开(公告)日：2009-05-21

申请号：US12024107

申请日：2008-01-31

申请人： Hiroyuki YOSHIMOTO ,  Nobuyuki Sugii ,  Shinichi Saito ,  Digh Hisamoto

发明人： Hiroyuki YOSHIMOTO ,  Nobuyuki Sugii ,  Shinichi Saito ,  Digh Hisamoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain.

摘要翻译： 针对反向MOSFET的栅极和积累的MOSFET中的每一个的电压变化分别测量具有多个栅极的场效应晶体管的容量栅极电压特性。 这些测量结果与从量子效应模型提供的数值模拟一起用于确定多个门和通道之间的平带电压。 接下来，通过使用一组用于测量容量的平带电压作为下积分极限，计算有效正常电场作为矢量线积分。 最后，根据源极 - 漏极路径中的电流 - 栅极电压特性测量和电容测量值计算出有效正常电场的迁移率，并将计算的迁移率代入源极和漏极之间的电流 - 电压曲线的方程式。

公开(公告)号：US20090052259A1

公开(公告)日：2009-02-26

申请号：US12194433

申请日：2008-08-19

申请人： Tsuyoshi ARIGANE ,  Digh Hisamoto ,  Yasuhiro Shimamoto

发明人： Tsuyoshi ARIGANE ,  Digh Hisamoto ,  Yasuhiro Shimamoto

IPC分类号： G11C11/34

CPC分类号： G11C5/14 ,  G11C5/025 ,  G11C5/063 ,  G11C16/0425 ,  G11C16/0483 ,  G11C16/10

摘要： A non-volatile semiconductor memory device is provided. A gate electrode configuring a memory cell is turned into floating state and a potential of a gate electrode adjacent thereto is changed, and reduce the potential of the gate electrode by this change of potential and the capacitive coupling. Furthermore, charge sharing is carried out by connecting two gate electrodes, and the voltage of the gate electrode is reduced by capacitive coupling with another gate electrode adjacent thereto, to largely reduce the potential of the gate electrode. Thereby, the voltage level generated by the charge pump circuit can be reduced. As a result, the size of the charge pump circuit can be reduced, or the circuit itself can be eliminated, resulting in reduction of the chip area.

摘要翻译： 提供非易失性半导体存储器件。 构成存储单元的栅电极变为浮置状态，并且与其相邻的栅电极的电位改变，并且通过电位和电容耦合的这种改变来降低栅电极的电位。 此外，通过连接两个栅电极进行电荷共享，并且通过与与其相邻的另一个栅电极的电容耦合来减小栅电极的电压，从而大大减小栅电极的电位。 由此，可以降低由电荷泵电路产生的电压电平。 结果，可以减小电荷泵电路的尺寸，或者可以消除电路本身，从而减少芯片面积。