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251 条记录 (耗时 0.06 秒)

    Image-forming apparatus and image-forming method
    71.
    发明授权
    Image-forming apparatus and image-forming method 失效
    图像形成装置和图像形成方法

    公开(公告)号：US06934484B2

    公开(公告)日：2005-08-23

    申请号：US10631727

    申请日：2003-08-01

    申请人： Koji Suzuki ,  Mitsuo Aoki ,  Hiroto Higuchi ,  Shinya Nakayama ,  Maiko Kondo ,  Bing Shu ,  Yasushi Koichi ,  Tadashi Kasai ,  Yutaka Takahashi

    发明人： Koji Suzuki ,  Mitsuo Aoki ,  Hiroto Higuchi ,  Shinya Nakayama ,  Maiko Kondo ,  Bing Shu ,  Yasushi Koichi ,  Tadashi Kasai ,  Yutaka Takahashi

    IPC分类号： G03G15/20

    CPC分类号： G03G15/2064

    摘要： In a copier which is an image-forming apparatus comprising a photoconductor 1, a developing apparatus 4, transfer apparatus 5 which transfers a toner image formed on the photoconductor 1 to a transfer material by heat and pressure using a transfer roller 52, and a fixing apparatus which fixes the toner image transferred to the transfer material, on the transfer material, a heater 56, temperature detection apparatus 57 and temperature control apparatus are provided which controls the temperature to within a range of from the glass transition temperature (Tg) to the softening temperature (Tm) of the toner, and lower than the fixing temperature of the fixing apparatus 7.

    摘要翻译： 在作为包括感光体1的图像形成装置的复印机中，显影装置4，使用转印辊52将通过热和压力将形成在感光体1上的调色剂图像转印到转印材料上的转印装置5和固定 提供了将转印到转印材料上的调色剂图像，转印材料，加热器56，温度检测装置57和温度控制装置固定的装置，其将温度控制在从玻璃化转变温度（Tg）到 调色剂的软化温度（Tm）低于定影装置7的定影温度。

    Fractional N frequency synthesizer
    74.
    发明授权
    Fractional N frequency synthesizer 失效
    分数N频率合成器

    公开(公告)号：US06873213B2

    公开(公告)日：2005-03-29

    申请号：US10261904

    申请日：2002-10-01

    申请人： Kazutoshi Tsuda ,  Yutaka Takahashi

    发明人： Kazutoshi Tsuda ,  Yutaka Takahashi

    IPC分类号： H03L7/197 ,  H03L7/08 ,  H03L7/18

    CPC分类号： H03L7/1976

    摘要： A frequency synthesizer (100) that may have reduced spurious noise caused by a voltage controlled oscillator (VCO) (4) output sneaking into an input side of a phase comparison circuit (1) has been disclosed. A beat frequency component that may be generated by mixing of a portion of a VCO output sneaking into an input side of a phase comparison circuit (1) through a reference signal (REF) or a comparison signal (SIG) may be shifted to a high frequency region by providing a modulator circuit (7) on a reference signal side or a comparison signal side. Thus, a low pass filter circuit (3) may provide attenuation to the spurious noise. In this way, spurious noise in the VCO output may be reduced.

    摘要翻译： 已经公开了可以将输出潜入相位比较电路（1）的输入侧的压控振荡器（VCO）（4）引起的具有降低的杂散噪声的频率合成器（100）。 可以通过将参考信号（REF）或比较信号（SIG）混合到相位比较电路（1）的输入侧的VCO输出的一部分混合而产生的拍频分量可以移位到高 通过在参考信号侧或比较信号侧提供调制器电路（7）。 因此，低通滤波器电路（3）可以对伪噪声提供衰减。 以这种方式，可以减小VCO输出中的杂散噪声。

    Vertical processing unit
    76.
    发明授权
    Vertical processing unit 有权
    垂直处理单元

    公开(公告)号：US6110286A

    公开(公告)日：2000-08-29

    申请号：US175433

    申请日：1998-10-20

    申请人： Seungho Oh ,  Katsutoshi Ishii ,  Toshiharu Nishimura ,  Yutaka Takahashi

    发明人： Seungho Oh ,  Katsutoshi Ishii ,  Toshiharu Nishimura ,  Yutaka Takahashi

    IPC分类号： H01L21/22 ,  C23C16/44 ,  C23C16/455 ,  C23C16/54 ,  C30B25/14 ,  H01L21/00 ,  H01L21/205 ,  H01L21/31 ,  C23C16/00

    CPC分类号： C23C16/45519 ,  C23C16/4401 ,  C23C16/54 ,  C30B25/14 ,  H01L21/67017

    摘要： A vertical processing unit 10 for semiconductor wafers has; a cylindrical processing chamber 2 having an opening 18 in an inside of an annular bottom surface, and a disk-shaped cap 6 having an annular abutting-surface 32 abutting on the annular bottom surface of the chamber. A mounting-surface 6p formed on the inside of the annular abutting-surface 32. A wafer-boat 8 for holding a wafer W to be processed is mounted on the mounting-surface 6p of the cap 6. The abutting-surface 32 has an annular groove 34A formed therein. An inert gas supply passgeway 38 is provided in communication with the annular groove 34A for supplying an inert gas into the annular groove 34A through a header 16. An ejection opening 36 for ejecting an inert gas is provided on the inner side of the annular groove 34A for communicating the annular groove 34A and the interior of the processing chamber 2. Owing to the active leaking of the nitrogen (N.sub.2) gas into the interior of the processing chamber 2 through the ejection opening 36, the corrosive gas as a processing gas in the processing chamber 2 does not leak out, so that corrosion or rusting of the equipment around the processing chamber 2 is prevented.

    摘要翻译： 用于半导体晶片的垂直处理单元10具有： 在环形底面的内侧具有开口18的圆筒状的处理室2和与该室的环状底面邻接的环状的抵接面32的圆盘状的盖6。 安装表面6p，形成在环形邻接表面32的内侧。用于保持待处理晶片W的晶片舟8安装在盖6的安装表面6p上。邻接表面32具有 形成在其中的环形槽34A。 惰性气体供给接头38与环形槽34A连通，用于通过集管16将惰性气体供给到环形槽34A中。用于喷射惰性气体的喷射口36设置在环形槽34A的内侧 用于使环形槽34A和处理室2的内部连通。由于氮气（N 2）气体通过喷射开口36有效地泄漏到处理室2的内部，腐蚀性气体作为处理气体 处理室2不会泄漏，从而防止了处理室2周围的设备的腐蚀或生锈。

    Clock control circuits, systems and methods
    77.
    发明授权
    Clock control circuits, systems and methods 失效
    时钟控制电路，系统和方法

    公开(公告)号：US5842005A

    公开(公告)日：1998-11-24

    申请号：US854045

    申请日：1997-05-08

    申请人： James J. Walsh ,  Joseph Joe ,  Ian Chen ,  Yutaka Takahashi

    发明人： James J. Walsh ,  Joseph Joe ,  Ian Chen ,  Yutaka Takahashi

    IPC分类号： G06F1/26 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G06F1/16 ,  G06F1/32 ,  G06F3/00 ,  G06F9/30 ,  G06F1/08

    CPC分类号： G06F1/1632 ,  G06F1/10 ,  G06F1/32

    摘要： A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU.sub.-- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU.sub.-- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.

    摘要翻译： 微处理器设备（102）包括具有时钟输入的中央处理单元（702），时钟脉冲的时钟发生器（OSC，PLL），具有提供时钟控制信号（SUSP）的输出的逻辑电路（708） 以及由时钟脉冲馈送并且具有耦合到中央处理单元的时钟输入的时钟门输出（CPU-CLK）的时钟门（3610）。 时钟门（3610）响应时钟控制信号（SUSP），以防止所述时钟脉冲（CPU-CLK）在所述时钟控制信号的变化的一个时钟周期内到达中央处理单元。 还公开了其他装置，系统和方法。

    Clock control circuits, systems and methods
    78.
    发明授权
    Clock control circuits, systems and methods 失效
    时钟控制电路，系统和方法

    公开(公告)号：US5754837A

    公开(公告)日：1998-05-19

    申请号：US363198

    申请日：1994-12-22

    申请人： James J. Walsh ,  Joseph Joe ,  Ian Chen ,  Yutaka Takahashi

    发明人： James J. Walsh ,  Joseph Joe ,  Ian Chen ,  Yutaka Takahashi

    IPC分类号： G06F1/26 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G06F1/16 ,  G06F1/32 ,  G06F3/00 ,  G06F9/30 ,  G06F1/08

    CPC分类号： G06F1/1632 ,  G06F1/10 ,  G06F1/32

    摘要： A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU.sub.-- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU.sub.-- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.

    摘要翻译： 微处理器设备（102）包括具有时钟输入的中央处理单元（702），时钟脉冲的时钟发生器（OSC，PLL），具有提供时钟控制信号（SUSP）的输出的逻辑电路（708） 以及由时钟脉冲馈送并且具有耦合到中央处理单元的时钟输入的时钟门输出（CPU-CLK）的时钟门（3610）。 时钟门（3610）响应时钟控制信号（SUSP），以防止所述时钟脉冲（CPU-CLK）在所述时钟控制信号的变化的一个时钟周期内到达中央处理单元。 还披露了其他设备，系统和方法。

    Level convertor
    80.
    发明授权
    Level convertor 失效
    液位转换器

    公开(公告)号：US5748024A

    公开(公告)日：1998-05-05

    申请号：US530483

    申请日：1995-09-19

    申请人： Yutaka Takahashi ,  Manabu Niiyama ,  Yoshiki Goto

    发明人： Yutaka Takahashi ,  Manabu Niiyama ,  Yoshiki Goto

    IPC分类号： H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/02

    CPC分类号： H03K19/018521

    摘要： A level convertor is provided between circuits, which act with different power supply voltages, respectively, and converts a first voltage level of an output of a circuit to a second voltage level, which corresponds to an operational voltage level of another circuit. The level convertor comprises a level shift circuit, which receives the first voltage level and outputs an output of the second voltage level, and a buffer circuit, which receives the output of the second level and a control signal, and fixes the output of the second voltage level to a low logic level, when the control signal is a low logic level. The control signal may be used to set a timing for registering the data to a register, avoiding data in an instable state when power is supplied, from being registered to the register.

    摘要翻译： 电路之间提供电平转换器，其分别作用于不同的电源电压，并且将电路的输出的第一电压电平转换成对应于另一个电路的工作电压电平的第二电压电平。 电平转换器包括电平移位电路，其接收第一电压电平并输出第二电压电平的输出;以及缓冲电路，其接收第二电平的输出和控制信号，并且固定第二电平的输出 当控制信号为低逻辑电平时，电压电平变为低逻辑电平。 控制信号可以用于设置将数据登记到寄存器的定时，避免在供电时处于不稳定状态的数据从注册到寄存器。