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71.发明授权Systems and methods for mitigating variances on a patterned wafer using a prediction model 有权使用预测模型减轻图案化晶片上的方差的系统和方法公开(公告)号：US07297453B2
公开(公告)日：2007-11-20
申请号：US11394900
申请日：2006-03-31
CPC分类号： G03F1/84 , G03F1/36 , Y10S430/146
摘要： Disclosed are systems and methods for mitigating variances (e.g., critical dimension variances) on a patterned wafer are provided. In general, variances of a patterned wafer are predicted using one or more reticle fabrication and/or wafer processing models. The predicted variances are used to modify selected transparent portions of the reticle that is to be used to produce the patterned wafer. In a specific implementation, an optical beam, such as a femto-second laser, is applied to the reticle at a plurality of embedded positions, and the optical beam is configured to form specific volumes of altered optical properties within the transparent material of the reticle at the specified positions. These reticle volumes that are created at specific positions of the reticle result in varying amounts of light transmission or dose through the reticle at such specific positions so as to mitigate the identified variances on a wafer that is patterned using the modified reticle.
摘要翻译： 公开了用于减轻图案化晶片上的方差（例如，临界尺寸方差）的系统和方法。 通常，使用一个或多个掩模版制造和/或晶片处理模型预测图案化晶片的变化。 预测的方差用于修改用于产生图案化晶片的掩模版的所选透明部分。 在具体实现中，诸如毫微微秒激光器的光束在多个嵌入位置被施加到掩模版，并且光束被配置为在掩模版的透明材料内形成改变的光学特性的特定体积 在指定位置。 在掩模版的特定位置处产生的这些掩模版体积在这样的特定位置处导致通过掩模版的光透射或剂量的变化量，以便减轻使用修改的掩模版图案化的晶片上识别的方差。
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公开(公告)号：US20120256559A1
公开(公告)日：2012-10-11
申请号：US13081734
申请日：2011-04-07
申请人： Guoheng Zhao , Ady Levy , Alex Salnik , Mehdi Vaez-Iravani , Lena Nicolaides , Samuel S.H. Ngai
发明人： Guoheng Zhao , Ady Levy , Alex Salnik , Mehdi Vaez-Iravani , Lena Nicolaides , Samuel S.H. Ngai
IPC分类号： H05B37/02
CPC分类号： H05B33/0803
摘要： An apparatus for illuminating a target surface, the apparatus having a plurality of LED arrays, where each of the arrays has a plurality of individually addressable LEDs, and where at least one of the arrays is disposed at an angle of between about forty-five degrees and about ninety degrees relative to the target surface, where all of the arrays supply light into a light pipe, the light pipe having interior walls made of a reflective material, where light exiting the light pipe illuminates the target surface, and a controller for adjusting an intensity of the individually addressable light sources.
摘要翻译： 一种用于照射目标表面的装置，该装置具有多个LED阵列，其中每个阵列具有多个独立可寻址的LED，并且其中至少一个阵列以大约四十五度之间的角度设置 并且相对于目标表面大约九十度，其中所有的阵列将光提供到光管中，光管具有由反射材料制成的内壁，其中离开光管的光照射目标表面，以及用于调节的控制器 独立寻址光源的强度。
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公开(公告)号：US07767956B2
公开(公告)日：2010-08-03
申请号：US12328123
申请日：2008-12-04
申请人： Suresh Lakkapragada , Kyle A. Brown , Matt Hankinson , Ady Levy
发明人： Suresh Lakkapragada , Kyle A. Brown , Matt Hankinson , Ady Levy
CPC分类号： G03F7/70558 , G01N21/47 , G01N21/956 , G03F7/70625 , G03F7/70641 , H01L22/20 , H01L2924/0002 , Y10S414/135 , H01L2924/00
摘要： Methods and systems for evaluating and controlling a lithography process are provided. For example, a method for reducing within wafer variation of a critical metric of a lithography process may include measuring at least one property of a resist disposed upon a wafer during the lithography process. A critical metric of a lithography process may include, but may not be limited to, a critical dimension of a feature formed during the lithography process. The method may also include altering at least one parameter of a process module configured to perform a step of the lithography process to reduce within wafer variation of the critical metric. The parameter of the process module may be altered in response to at least the one measured property of the resist.
摘要翻译： 提供了用于评估和控制光刻工艺的方法和系统。 例如，用于减小光刻工艺的关键度量的晶片间变化的方法可以包括在光刻工艺期间测量设置在晶片上的抗蚀剂的至少一种性质。 光刻工艺的关键度量可以包括但不限于在光刻工艺期间形成的特征的临界尺寸。 该方法还可以包括改变被配置为执行光刻处理步骤的处理模块的至少一个参数以减少关键度量的晶片变化。 响应于抗蚀剂的至少一个测量性质，可以改变工艺模块的参数。
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公开(公告)号：US07175945B2
公开(公告)日：2007-02-13
申请号：US11084556
申请日：2005-03-16
申请人： Walter Dean Mieher , Daniel Wack , Ady Levy
发明人： Walter Dean Mieher , Daniel Wack , Ady Levy
CPC分类号： G03F7/70641 , G03F1/28 , G03F1/44 , G06K7/0095
摘要： Methods and device structures used to determine the focus quality of a photolithographic pattern or a photolithographic system are disclosed. One aspect of the invention relates to focus masking structures configured to form focus patterns that contain focus information relating to the focus quality. The focus masking structures generally include a plurality of parallel source lines that are separated by alternating phase shift zones. Another aspect of the invention relates to focus patterns that change with changes in focus. The focus patterns generally include a plurality of periodic structures that form measurable shifts therebetween corresponding to the sign and magnitude of defocus. Another aspect of the invention relates to a method of determining the focus quality of a photolithographic pattern or a photolithographic system. The method generally includes: providing a focus masking structure, forming a focus pattern on a work piece with the focus masking structure, and obtaining focus information from the focus pattern. The focus information may be obtained using a variety of techniques, as for example, scatterometry techniques, scanning techniques, imaging techniques, phase based techniques, and the like.
摘要翻译： 公开了用于确定光刻图案或光刻系统的焦点质量的方法和装置结构。 本发明的一个方面涉及被配置为形成聚焦图案的聚焦掩模结构，其包含与焦点质量相关的焦点信息。 聚焦掩模结构通常包括由交替的相移区域分开的多个平行的源极线。 本发明的另一方面涉及随焦点变化而变化的聚焦图案。 聚焦图案通常包括多个周期性结构，其在散焦的符号和大小之间形成可测量的偏移。 本发明的另一方面涉及一种确定光刻图案或光刻系统的焦点质量的方法。 该方法通常包括：提供聚焦掩蔽结构，在聚焦掩模结构的工件上形成聚焦图案，以及从焦点图案获得聚焦信息。 可以使用各种技术获得焦点信息，例如散射测量技术，扫描技术，成像技术，基于相位的技术等。
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公开(公告)号：US20060234145A1
公开(公告)日：2006-10-19
申请号：US11394177
申请日：2006-03-29
申请人： Sterling Watson , Ady Levy , Chris Mack , Stanley Stokowski , Zain Saidin
发明人： Sterling Watson , Ady Levy , Chris Mack , Stanley Stokowski , Zain Saidin
CPC分类号： G03F1/84 , Y10S430/146
摘要： Disclosed are techniques for determining and correcting reticle variations using a reticle global variation map generated by comparing a set of measured reticle parameters to a set of reference reticle parameters. The measured reticle parameters are obtained by reticle inspection, and the variation map identifies reticle regions and associated levels of correction. In one embodiment, the variation data is communicated to a system which modifies the reticle by embedding scattering centers within the reticle at identified reticle regions, thereby improving the variations. In another embodiment the variation data is transferred to a wafer stepper or scanner which in turn modifies the conditions under which the reticle is used to manufacture wafers, thereby compensating for the variations and producing wafers that are according to design.
摘要翻译： 公开了用于使用通过将测量的标线参数的集合与一组参考掩模版参数进行比较而生成的光罩全局变化图来确定和校正光罩变化的技术。 通过掩模版检查获得测量的掩模版参数，并且变化图识别标线区域和相关联的校正水平。 在一个实施例中，将变化数据传送到通过在标定的标线区域内的散射中心嵌入来修改掩模版的系统，从而改善变化。 在另一个实施例中，变化数据被传送到晶片步进器或扫描器，该晶片步进器或扫描器又改变了使用掩模版制造晶片的条件，从而补偿了根据设计的变化和生产晶片。
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公开(公告)号：US06486954B1
公开(公告)日：2002-11-26
申请号：US09654318
申请日：2000-09-01
申请人： Walter Dean Mieher , Ady Levy
发明人： Walter Dean Mieher , Ady Levy
IPC分类号： G01B1127
CPC分类号： G03F7/70633 , G01B11/002
摘要： An alignment mark comprising a first test zone and a second test zone for measuring the relative position between different layers of a semiconductor device. The alignment mark is used to determine the overlay error between layers of a semiconductor wafer while minimizing measurement inaccuracies caused by semiconductor manufacturing processes. The first test zone includes two sections, one in which test structures are formed on one layer and a second in which test structures are formed on a second layer. Each of these test structures is composed of smaller sub-structures. The second test zone includes two similar sections that are also composed of smaller sub-structures. The first and second test zones are configured so that the section of each test zone formed one layer is adjacent to the section of the other test zone that is formed on the other layer. By forming each of the periodic structures with smaller sized sub-structures, a more accurate measurement of any alignment error may be obtained. Another aspect of the present invention pertains to a method of utilizing the alignment mark so that an overlay measurement may be obtained.
摘要翻译： 对准标记包括第一测试区和第二测试区，用于测量半导体器件的不同层之间的相对位置。 对准标记用于确定半导体晶片的层之间的重叠误差，同时最小化由半导体制造工艺引起的测量不准确。 第一测试区包括两个部分，一个测试结构形成在一个层上，另一个测试结构形成在第二层上。 这些测试结构中的每一个都由较小的子结构组成。 第二测试区域包括两个类似的部分，它们也由较小的子结构组成。 第一和第二测试区被配置成使得形成一层的每个测试区的部分与形成在另一层上的另一测试区的部分相邻。 通过用较小尺寸的子结构形成每个周期性结构，可以获得任何对准误差的更准确的测量。 本发明的另一方面涉及一种利用对准标记以便可以获得覆盖测量的方法。
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公开(公告)号：US07989729B1
公开(公告)日：2011-08-02
申请号：US12045724
申请日：2008-03-11
CPC分类号： G01J1/08 , G01J1/0466 , G01J2005/0077 , H01L31/186 , Y02E10/50 , Y02P70/521 , Y10S136/29
摘要： An apparatus for both detecting and repairing a shunt defect in a solar cell substrate. A shunt detection module detects the shunt defect in the substrate, using at least one of lock-in thermography and current-voltage testing. A process diagnostic module determines whether the substrate should be passed without further processing by the apparatus, rejected without further processing by the apparatus, or repaired by the apparatus. A shunt repair module electrically isolates the shunt defect in the substrate. In this manner, a single apparatus can quickly check for shunts and make a determination as to whether the substrate is worth repairing. If it is worth repairing, then the apparatus can make the repairs to the substrate.
摘要翻译： 一种用于检测和修复太阳能电池基板中的分流缺陷的装置。 分流检测模块使用锁定热成像和电流 - 电压测试中的至少一种来检测衬底中的分流缺陷。 过程诊断模块确定衬底是否应该被通过而不被设备进一步处理，不经设备的进一步处理就被拒绝或被设备修复。 分流修复模块电隔离衬底中的分流缺陷。 以这种方式，单个装置可以快速检查分流并且确定基板是否值得修复。 如果值得修理，那么设备可以对基材进行维修。
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公开(公告)号：US07733111B1
公开(公告)日：2010-06-08
申请号：US12045734
申请日：2008-03-11
申请人： Guoheng Zhao , Bin-Ming B. Tsai , Mehdi Vaez-Iravani , Ady Levy , George H. Zapalac, Jr. , Samuel S. H. Ngai
发明人： Guoheng Zhao , Bin-Ming B. Tsai , Mehdi Vaez-Iravani , Ady Levy , George H. Zapalac, Jr. , Samuel S. H. Ngai
IPC分类号： G01R31/26
CPC分类号： H02S50/10 , F21S8/006 , F21Y2115/10
摘要： An apparatus for inducing a current in a solar cell substrate. A substrate receiving surface receives the substrate, and an array of a plurality of individually addressable light sources illuminates the substrate in a sequenced manner. A sequencer controls the sequenced manner of illumination of the substrate by the array. A front side electrical contact makes electrical contact to a front side of the substrate, and a back side electrical contact makes electrical contact to a back side of the substrate. A meter is electrically connected to the front side electrical contact and the back side electrical contact, and senses the current induced in the substrate during the sequenced illumination of the substrate.
摘要翻译： 一种用于在太阳能电池基板中感应电流的装置。 衬底接收表面接收衬底，并且多个可单独寻址的光源的阵列以顺序的方式照射衬底。 定序器通过阵列控制衬底的照明顺序。 前侧电触点与基板的前侧电接触，并且背面电触点与基板的背面进行电接触。 仪表电连接到前侧电触头和后侧电触点，并感测在衬底的顺序照明期间在衬底中感应的电流。
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公开(公告)号：US20060234139A1
公开(公告)日：2006-10-19
申请号：US11394901
申请日：2006-03-31
申请人： Sterling Watson , Ady Levy , Chris Mack , Stanley Stokowski , Zain Saidin , Larry Zurbrick
发明人： Sterling Watson , Ady Levy , Chris Mack , Stanley Stokowski , Zain Saidin , Larry Zurbrick
CPC分类号： G06K9/2063 , G03F1/72 , G03F1/84 , Y10S430/146
摘要： Disclosed are systems and methods for modifying a reticle. In general, inspection results from a plurality of wafers or prediction results from a lithographic model are used to individually decrease the dose or any other optical property at specific locations of the reticle. In one embodiment, any suitable optical property of the reticle is modified by an optical beam, such as a femto-second laser, at specific locations on the reticle so as to widen the process window for such optical property. Examples of optical properties include dose, phase, illumination angle, and birefringence. Techniques for adjusting optical properties at specific locations on a reticle using an optical beam may be practiced for other purposes besides widening the process window.
摘要翻译： 公开了用于修改掩模版的系统和方法。 通常，来自多个晶片的检查结果或来自光刻模型的预测结果被用于单独地减小光罩的特定位置处的剂量或任何其它光学特性。 在一个实施例中，掩模版的任何合适的光学性质通过光束（例如毫微微秒级激光器）在掩模版上的特定位置处被修改，以便加宽用于这种光学性质的工艺窗口。 光学性质的实例包括剂量，相位，照射角度和双折射率。 使用光束在光罩上的特定位置处调整光学特性的技术可以用于除加宽工艺窗口之外的其它目的。
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公开(公告)号：US06987572B2
公开(公告)日：2006-01-17
申请号：US10366838
申请日：2003-02-14
申请人： Suresh Lakkapragada , Kyle A. Brown , Matt Hankinson , Ady Levy
发明人： Suresh Lakkapragada , Kyle A. Brown , Matt Hankinson , Ady Levy
IPC分类号： G01B11/24
CPC分类号： G03F7/70558 , G01N21/47 , G01N21/956 , G03F7/70625 , G03F7/70641 , H01L22/20 , H01L2924/0002 , Y10S414/135 , H01L2924/00
摘要： Methods and systems for evaluating and controlling a lithography process are provided. For example, a method for reducing within wafer variation of a critical metric of a lithography process may include measuring at least one property of a resist disposed upon a wafer during the lithography process. A critical metric of a lithography process may include, but may not be limited to, a critical dimension of a feature formed during the lithography process. The method may also include altering at least one parameter of a process module configured to perform a step of the lithography process to reduce within wafer variation of the critical metric. The parameter of the process module may be altered in response to at least the one measured property of the resist.
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