公开(公告)号：US08122275B2

公开(公告)日：2012-02-21

申请号：US11843123

申请日：2007-08-22

申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

公开(公告)号：US20110221497A1

公开(公告)日：2011-09-15

申请号：US13019277

申请日：2011-02-01

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

IPC分类号： H03L7/00 ,  H03H11/26

CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

公开(公告)号：US07969215B1

公开(公告)日：2011-06-28

申请号：US12467681

申请日：2009-05-18

申请人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

发明人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

IPC分类号： H03L7/00

CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0805

摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

摘要翻译： 可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。 然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置，以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

公开(公告)号：US20080291758A1

公开(公告)日：2008-11-27

申请号：US11935310

申请日：2007-11-05

申请人： Michael H.M. Chu ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Andrew Bellis ,  Philip Clarke ,  Manoj B. Roge

发明人： Michael H.M. Chu ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Andrew Bellis ,  Philip Clarke ,  Manoj B. Roge

IPC分类号： G11C7/10

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  H03L7/06 ,  H03L7/0812

摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

摘要翻译： 用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中，输入信号可以被延迟与延迟设置相对应的量。 在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。

公开(公告)号：US07321518B1

公开(公告)日：2008-01-22

申请号：US10757928

申请日：2004-01-15

申请人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong

发明人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong

IPC分类号： G11C7/00 ,  G11C29/00 ,  G06F7/38 ,  H03K19/177

CPC分类号： H03K19/1776 ,  G11C29/802 ,  G11C2229/726 ,  H03K19/17764

摘要： An integrated circuit (IC) includes a redundancy feature. The redundancy feature is provided by a redundancy circuitry within the IC. The redundancy circuitry is configured to provide the redundancy by using a decoder circuitry. The decoder circuitry receives and decodes coded defect information from a set of circuit elements adapted to provide the coded defect information.

摘要翻译： 集成电路（IC）包括冗余特征。 冗余特性由IC内的冗余电路提供。 冗余电路被配置为通过使用解码器电路来提供冗余。 解码器电路从适于提供编码缺陷信息的一组电路元件接收并解码编码的缺陷信息。

公开(公告)号：US07205802B1

公开(公告)日：2007-04-17

申请号：US11349516

申请日：2006-02-03

申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

IPC分类号： H03L7/06

CPC分类号： H03K5/135 ,  H03K5/1252 ,  H03L7/0805 ,  H03L7/0814

摘要： A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.

摘要翻译： 一种用于在DDR应用中更新由延迟链接收的控制信号的方法和装置。 寄存器用于调节到延迟链的控制信号。 当信号没有通过延迟链时，寄存器仅更新延迟链上的信号。 此外，本发明涉及一种延迟电路，其使用彼此并联连接的多个PMOS和NMOS晶体管以及提供所需延迟的反相器。 提供的延迟是通过顺序关闭/接通一系列NMOS / PMOS晶体管对来实现的。

公开(公告)号：US07098690B2

公开(公告)日：2006-08-29

申请号：US11025774

申请日：2004-12-29

申请人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

发明人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： C07K16/28 ,  A61K2039/505 ,  C07K14/47

摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

摘要翻译： 用于逻辑阵列的I / O端子的可编程I / O元件适用于根据高速I / O模式（如双数据速率和零总线周转）进行工作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。 另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。 对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块为输出缓冲器的选通输入提供使能信号。 可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

公开(公告)号：US07091760B1

公开(公告)日：2006-08-15

申请号：US10788221

申请日：2004-02-25

申请人： Tzung-chin Chang ,  Chiakang Sung ,  Yan Chong ,  Henry Kim ,  Joseph Huang

发明人： Tzung-chin Chang ,  Chiakang Sung ,  Yan Chong ,  Henry Kim ,  Joseph Huang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： Circuits and methods are described for producing a DLL clock signal with adjustable phase shift using a processed control signal. In one embodiment of the invention, a DLL circuit is provided that includes a main and smaller variable delay circuits, a phase detector and an up down counter that provides a main control signal to adjust the delay by the main variable delay circuit. When the DLL circuit is locked, an arithmetic logic unit (ALU) produces a processed control signal based on the main control signal, an ALU control signal and an offset control signal, and the processed control signal is provided to the smaller variable delay circuit. By adjusting the ALU control and offset control signals, the phase shift introduced on the DLL control signal by the smaller variable delay circuit can be adjusted. In another embodiment of the invention, a second up down counter is used in place of an ALU for providing a dynamically adjustable phase shift in accordance with the principles of the present invention.

摘要翻译： 描述了用于使用处理的控制信号产生具有可调相移的DLL时钟信号的电路和方法。 在本发明的一个实施例中，提供一种DLL电路，其包括主要和较小的可变延迟电路，相位检测器和向上计数器，其提供主控制信号以通过主可变延迟电路来调整延迟。 当DLL电路被锁定时，算术逻辑单元（ALU）基于主控制信号，ALU控制信号和偏移控制信号产生处理的控制信号，并且处理的控制信号被提供给较小的可变延迟电路。 通过调整ALU控制和偏移控制信号，可以调整由较小的可变延迟电路引入到DLL控制信号上的相移。 在本发明的另一实施例中，根据本发明的原理，使用第二向上计数器来代替ALU来提供动态可调的相移。

公开(公告)号：US07030675B1

公开(公告)日：2006-04-18

申请号：US10932642

申请日：2004-08-31

申请人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

发明人： Bonnie I. Wang ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Khai Nguyen ,  Henry Kim

IPC分类号： H03H11/26

CPC分类号： H03K5/135 ,  H03K5/1252 ,  H03L7/0805 ,  H03L7/0814

摘要： A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.

摘要翻译： 一种用于在DDR应用中更新由延迟链接收的控制信号的方法和装置。 寄存器用于调节到延迟链的控制信号。 当信号没有通过延迟链时，寄存器仅更新延迟链上的信号。 此外，本发明涉及一种延迟电路，其使用彼此并联连接的多个PMOS和NMOS晶体管以及提供所需延迟的反相器。 提供的延迟是通过顺序关闭/接通一系列NMOS / PMOS晶体管对来实现的。

公开(公告)号：US06946872B1

公开(公告)日：2005-09-20

申请号：US10623394

申请日：2003-07-18

申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/1774 ,  H03K19/17744

摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。