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176 条记录 (耗时 0.064 秒)

    Resistive cross-point architecture for robust data representation with arbitrary precision
    71.
    发明授权
    Resistive cross-point architecture for robust data representation with arbitrary precision 有权
    用于具有任意精度的鲁棒数据表示的电阻式交叉点架构

    公开(公告)号：US09466362B2

    公开(公告)日：2016-10-11

    申请号：US14824782

    申请日：2015-08-12

    申请人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

    发明人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

    IPC分类号： G11C5/06 ,  G11C13/00

    CPC分类号： G11C13/0026 ,  G11C5/06 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/77 ,  G11C2213/79

    摘要： This disclosure relates generally to resistive memory systems. The resistive memory systems may be utilized to implement neuro-inspired learning algorithms with full parallelism. In one embodiment, a resistive memory system includes a cross point resistive network and switchable paths. The cross point resistive network includes variable resistive elements and conductive lines. The conductive lines are coupled to the variable resistive elements such that the conductive lines and the variable resistive elements form the cross point resistive network. The switchable paths are connected to the conductive lines so that the switchable paths are operable to selectively interconnect groups of the conductive lines such that subsets of the variable resistive elements each provide a combined variable conductance. With multiple resistive elements in the subsets, process variations in the conductances of the resistive elements average out. As such, learning algorithms may be implemented with greater precision using the cross point resistive network.

    摘要翻译： 本公开一般涉及电阻式存储器系统。 电阻式存储器系统可用于实现具有完全并行性的神经启发式学习算法。 在一个实施例中，电阻式存储器系统包括交叉点电阻网络和可切换路径。 交叉点电阻网络包括可变电阻元件和导线。 导线耦合到可变电阻元件，使得导线和可变电阻元件形成交叉电阻网络。 可切换路径连接到导线，使得可切换路径可操作以选择性地互连导电线组，使得可变电阻元件的子集各自提供组合的可变电导。 在子集中具有多个电阻元件，电阻元件的电导的工艺变化平均。 因此，可以使用交叉点电阻网络以更高的精度来实现学习算法。

    Method and system for lithography process-window-maximixing optical proximity correction
    72.
    发明授权
    Method and system for lithography process-window-maximixing optical proximity correction 有权
    光刻过程窗口最大化光学邻近校正的方法和系统

    公开(公告)号：US09360766B2

    公开(公告)日：2016-06-07

    申请号：US12642436

    申请日：2009-12-18

    申请人： Jun Ye ,  Yu Cao ,  Hanying Feng

    发明人： Jun Ye ,  Yu Cao ,  Hanying Feng

    IPC分类号： G06F17/50 ,  G03F7/20 ,  G03F1/00 ,  G03F1/36

    CPC分类号： G03F1/36 ,  G03F1/144 ,  G03F7/70441 ,  G03F7/705 ,  G06F17/5081 ,  G06F2217/12

    摘要： The present invention relates to an efficient OPC method of increasing imaging performance of a lithographic process utilized to image a target design having a plurality of features. The method includes the steps of determining a function for generating a simulated image, where the function accounts for process variations associated with the lithographic process; and optimizing target gray level for each evaluation point in each OPC iteration based on this function. In one given embodiment, the function is approximated as a polynomial function of focus and exposure, R(ε, f )=P0+f2·Pb with a threshold of T+Vε for contours, where P0 represents image intensity at nominal focus, f represents the defocus value relative to the nominal focus, ε represents the exposure change, V represents the scaling of exposure change, and parameter “Pb” represents second order derivative images. In another given embodiment, the analytical optimal gray level is given for best focus with the assumption that the probability distribution of focus and exposure variation is Gaussian.

    摘要翻译： 本发明涉及一种提高用于成像具有多个特征的目标设计的光刻工艺的成像性能的有效OPC方法。 该方法包括以下步骤：确定用于产生模拟图像的功能，其中该功能考虑到与光刻工艺相关联的工艺变化; 并基于此功能对每个OPC迭代中的每个评估点优化目标灰度级。 在一个给定的实施例中，函数近似为焦点和曝光的多项式函数，R（＆egr; f）= P0 + f2·Pb，阈值为T + V＆egr; 对于轮廓，其中P0表示标称焦点处的图像强度，f表示相对于标称焦点的散焦值， 表示曝光变化，V表示曝光变化的缩放，参数“Pb”表示二阶导数图像。 在另一个给定的实施例中，假设聚焦和曝光变化的概率分布为高斯，给出最佳聚焦的分析最佳灰度级。

    Computational process control
    73.
    发明授权
    Computational process control 有权
    计算过程控制

    公开(公告)号：US08856694B2

    公开(公告)日：2014-10-07

    申请号：US13481564

    申请日：2012-05-25

    申请人： Jun Ye ,  Yu Cao ,  James Patrick Koonmen

    发明人： Jun Ye ,  Yu Cao ,  James Patrick Koonmen

    IPC分类号： G06F17/50 ,  G05B13/04 ,  G03F7/20

    CPC分类号： G03F7/70525 ,  B29C64/386 ,  G03F9/7096 ,  G05B13/04

    摘要： The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.

    摘要翻译： 本发明提供了计算过程控制（CPC）领域的许多创新。 CPC通过分析光刻设备/工艺的时间漂移​​，在芯片制造周期中提供独特的诊断功能，并为实现光刻设备/工艺的性能稳定性提供了解决方案。 本发明的实施例通过保持光刻设备的性能和/或基本上接近预定义基线条件的光刻工艺的参数来实现优化的工艺窗口和更高的产量。 这通过使用光刻过程模拟模型将测量的时间漂移​​与基线性能进行比较来完成。 一旦制造，CPC通过利用晶片计量技术和反馈回路来优化扫描仪的特定图案或掩模版，以及监视和控制其他方面的覆盖和/或CD均匀性（CDU）性能，以持续保持系统接近 基线条件。

    Lens heating compensation systems and methods
    76.
    发明授权
    Lens heating compensation systems and methods 有权
    镜头加热补偿系统及方法

    公开(公告)号：US08570485B2

    公开(公告)日：2013-10-29

    申请号：US12475071

    申请日：2009-05-29

    申请人： Jun Ye ,  Peng Liu ,  Yu Cao

    发明人： Jun Ye ,  Peng Liu ,  Yu Cao

    IPC分类号： G03B27/52

    CPC分类号： G03F7/70441 ,  G03F7/70266 ,  G03F7/705 ,  G03F7/70533 ,  G03F7/706 ,  G03F7/70891 ,  G06F17/50

    摘要： Methods for calibrating a photolithographic system are disclosed. A cold lens contour for a reticle design and at least one hot lens contour for the reticle design are generated from which a process window is defined. Aberrations induced by a lens manipulator are characterized in a manipulator model and the process window is optimized using the manipulator model. Aberrations are characterized by identifying variations in critical dimensions caused by lens manipulation for a plurality of manipulator settings and by modeling behavior of the manipulator as a relationship between manipulator settings and aberrations. The process window may be optimized by minimizing a cost function for a set of critical locations.

    摘要翻译： 公开了用于校准光刻系统的方法。 生成用于掩模版设计的冷透镜轮廓和用于掩模版设计的至少一个热透镜轮廓，由此定义处理窗口。 由透镜操纵器诱导的畸变在机械手模型中表征，并且使用机械手模型优化过程窗口。 像差的特征在于识别由多个操纵器设置的透镜操纵引起的关键尺寸的变化，以及通过将操纵器的行为建模为机械手设置和像差之间的关系。 可以通过最小化一组关键位置的成本函数来优化过程窗口。

    Predictive modeling of contact and via modules for advanced on-chip interconnect technology
    78.
    发明授权
    Predictive modeling of contact and via modules for advanced on-chip interconnect technology 失效
    用于高级片上互连技术的接触和通孔模块的预测建模

    公开(公告)号：US08483997B2

    公开(公告)日：2013-07-09

    申请号：US12493110

    申请日：2009-06-26

    申请人： Xia Li ,  Wei Zhao ,  David Bang ,  Yu Cao ,  Seung H. Kang ,  Matthew Nowak

    发明人： Xia Li ,  Wei Zhao ,  David Bang ,  Yu Cao ,  Seung H. Kang ,  Matthew Nowak

    IPC分类号： G06F7/60

    CPC分类号： G06F17/5036

    摘要： A computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). Code executes on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure. The BEOL structure can be a contact or a via. The layers of the contact/via include an inner filling material and an outer liner. The code accounts for a width scatter effect of the inner filling material, as well as a slope profile of the contact/via.

    摘要翻译： 计算机程序产品估计半导体集成电路（IC）的后端（BEOL）结构的性能。 代码在计算机上执行，以基于特定于BEOL结构的多个层的输入数据来动态地预测BEOL结构的电阻。 BEOL结构可以是一个触点或通孔。 接触/通孔的层包括内部填充材料和外部衬垫。 该代码考虑了内部填充材料的宽度散射效应，以及接触/通孔的斜率分布。

    FAST PARALLEL TEST OF SRAM ARRAYS
    79.
    发明申请
    FAST PARALLEL TEST OF SRAM ARRAYS 有权
    SRAM阵列的快速并行测试

    公开(公告)号：US20130111282A1

    公开(公告)日：2013-05-02

    申请号：US13808438

    申请日：2011-07-19

    申请人： Lawrence T. Clark ,  Yu Cao

    发明人： Lawrence T. Clark ,  Yu Cao

    IPC分类号： G11C29/08

    CPC分类号： G11C29/08 ,  G11C11/41 ,  G11C29/28 ,  G11C29/40 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/2602

    摘要： Systems and methods for performing parallel test operations on Static Random Access Memory (SRAM) cells are disclosed. In general, each parallel test operation is a test operation performed on a block of the SRAM cells in parallel, or simultaneously. In one embodiment, the SRAM cells are arranged into multiple rows and multiple columns where the columns are further arranged into one or more column groups. The block of the SRAM cells for each parallel test operation includes SRAM cells in two or more of the rows, SRAM cells in two or more columns in the same column group, or both SRAM cells in two or more rows and SRAM cells in two or more columns in the same column group.

    摘要翻译： 公开了用于在静态随机存取存储器（SRAM）单元上执行并行测试操作的系统和方法。 通常，每个并行测试操作是对SRAM单元的块并行或同时执行的测试操作。 在一个实施例中，SRAM单元被布置成多行和多列，其中列进一步布置成一个或多个列组。 用于每个并行测试操作的SRAM单元的块包括两行或多行中的SRAM单元，同一列组中的两列或更多列中的SRAM单元，或两行或多行中的两个SRAM单元或两个或更多行中的SRAM单元 更多列在同一列组中。