公开(公告)号：US20160379701A1

公开(公告)日：2016-12-29

申请号：US15257085

申请日：2016-09-06

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Keisuke NAKATSUKA ,  Tadashi MIYAKAWA ,  Katsuhiko HOYA ,  Takeshi HAMAMOTO ,  Hiroyuki TAKENAKA

IPC分类号： G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/08

CPC分类号： G11C11/1695 ,  G11C5/025 ,  G11C5/04 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

摘要： According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.

摘要翻译： 根据一个实施例，磁阻存储器件包括具有包括第一方向的第一表面的衬底; 和各自具有可切换电阻的存储元件。 沿着第一方向排列的第一列存储元件不同于在第一方向上的存储元件的位置处沿着第一方向排列的相邻的第二列存储元件。

公开(公告)号：US09524765B2

公开(公告)日：2016-12-20

申请号：US14460626

申请日：2014-08-15

申请人： QUALCOMM Incorporated

发明人： Yu Lu ,  Seung Hyuk Kang

IPC分类号： G11C11/16 ,  H01L27/22 ,  G11C7/24

CPC分类号： G11C11/1673 ,  G11C7/24 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1695 ,  G11C2213/78 ,  H01L27/228

摘要： An apparatus includes a first magnetic tunnel junction (MTJ) device of a differential MTJ pair. The apparatus further includes a second MTJ device of the differential MTJ pair. The first MTJ device includes a sense layer having a high coercivity portion.

摘要翻译： 一种装置包括差分MTJ对的第一磁隧道结（MTJ）装置。 该装置还包括差分MTJ对的第二MTJ装置。 第一MTJ装置包括具有高矫顽力部分的感测层。

公开(公告)号：US20160173289A1

公开(公告)日：2016-06-16

申请号：US14570910

申请日：2014-12-15

申请人： Honeywell International Inc.

发明人： Michael A. Smith

IPC分类号： H04L9/32 ,  G06F13/16 ,  G11C14/00

CPC分类号： H04L9/3278 ,  G06F13/1636 ,  G06F13/1689 ,  G09C1/00 ,  G11C8/12 ,  G11C11/165 ,  G11C11/1695 ,  G11C2029/4402

摘要： In some examples, a first delay path and a second delay path may each be configured to receive a signal as an input signal at the same time, propagate the input a plurality of MRAM cells, and output the propagated input signal for an arbiter. The arbiter may be configured to output a response value based at least in part on a relative order of arrival of the propagated input signals from the first and second delay paths.

摘要翻译： 在一些示例中，第一延迟路径和第二延迟路径可以各自被配置为同时接收作为输入信号的信号，传播多个MRAM单元的输入，并输出用于仲裁器的传播的输入信号。 仲裁器可以被配置为至少部分地基于来自第一和第二延迟路径的传播的输入信号的相对顺序输出响应值。

公开(公告)号：US20160154732A1

公开(公告)日：2016-06-02

申请号：US14988558

申请日：2016-01-05

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Ryousuke Takizawa

IPC分类号： G06F12/02 ,  G06F3/06

CPC分类号： G06F12/0238 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/1416 ,  G06F12/1425 ,  G06F12/1441 ,  G06F2212/1016 ,  G06F2212/202 ,  G11C7/1009 ,  G11C7/24 ,  G11C8/08 ,  G11C8/20 ,  G11C11/1695

摘要： A memory includes a cell array including memory cells storing data, and a write driver writing data to the cells. A write driver performs or does not perform writing of write data according to write mask data input along with the write data. A multiplexer selectively outputs a write protect signal or the write mask data. The write protect signal is fixed to a command prohibiting the write data from being written. The command is included in the write mask data. A write protect controller controls the multiplexer to output the write protect signal when an address of a write protect area in the cell array matches an address of the write data. The write protect controller controls the multiplexer to output the write mask data as it is when the address of the write protect area in the cell array does not match the address of the write data.

摘要翻译： 存储器包括包括存储数据的存储单元的单元阵列，以及写入驱动器向单元写入数据。 写入驱动器根据与写入数据一起输入的写入掩码数据执行或不执行写入数据的写入。 复用器选择性地输出写保护信号或写掩码数据。 写保护信号固定为禁止写入数据写入的命令。 该命令包含在写掩码数据中。 写保护控制器控制多路复用器输出写保护信号，当单元阵列中写保护区的地址与写入数据的地址匹配时。 写保护控制器控制多路复用器以当单元阵列中的写保护区域的地址与写数据的地址不匹配时输出写掩码数据。

公开(公告)号：US09142277B2

公开(公告)日：2015-09-22

申请号：US14038720

申请日：2013-09-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jinhyun Kim ,  Dogeun Kim

IPC分类号： G11C11/16 ,  G11C7/04 ,  G11C13/00

CPC分类号： G11C11/1673 ,  G11C7/04 ,  G11C11/165 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1695 ,  G11C13/0007 ,  G11C13/004

摘要： A semiconductor memory device is provided which includes a memory cell array including magnetic memory cells arranged in a matrix form of rows and columns and connected with bit lines and a source line; and a temperature sensing unit configured to generate a temperature sensing signal by sensing a temperature of the memory cell array. A memory controller, constituting a memory system together with the semiconductor memory device, may control read and write operations of the semiconductor memory device differently according to the temperature sensing signal of the temperature sensing unit.

摘要翻译： 提供一种半导体存储器件，其包括存储单元阵列，该存储单元阵列包括以行和列的矩阵形式布置并与位线和源极线连接的磁存储单元; 以及温度感测单元，被配置为通过感测存储单元阵列的温度来产生温度感测信号。 与半导体存储器件一起构成存储器系统的存储器控​​制器可以根据温度检测单元的温度感测信号来控制半导体存储器件的读取和写入操作。

公开(公告)号：US09058886B2

公开(公告)日：2015-06-16

申请号：US13966151

申请日：2013-08-13

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Tadashi Miyakawa

IPC分类号： G11C5/14 ,  G11C11/16 ,  H02H3/20

CPC分类号： G11C11/1695 ,  G11C5/147 ,  H02H3/20 ,  H02H9/046

摘要： A power supply circuit includes a first circuit connected to a first line, to which a power supply voltage is applied, and a second line, and a power supply clamp circuit connected to the first and second lines. The power supply clamp circuit includes a current path circuit which connects the first and the second lines to each other, and a control circuit which outputs a control signal to the current path circuit. The current path circuit includes a transistor and a diode group. The power supply clamp circuit is driven during a period in which a first voltage is applied to the first line and controls a potential of the first line so as to become a potential lower than the first voltage.

摘要翻译： 电源电路包括连接到施加电源电压的第一线路的第一电路和第二线路，以及连接到第一线路和第二线路的电源钳位电路。 电源钳位电路包括将第一和第二线路相互连接的电流路径电路，以及向电流路径电路输出控制信号的控制电路。 电流路径电路包括晶体管和二极管组。 电源钳位电路在向第一线路施加第一电压并且控制第一线路的电位以便变为低于第一电压的电位的时段内被驱动。

公开(公告)号：US09030200B2

公开(公告)日：2015-05-12

申请号：US13618163

申请日：2012-09-14

申请人： James G. Deak

发明人： James G. Deak

IPC分类号： G01R33/12 ,  G11C11/16

CPC分类号： G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1695

摘要： A spin dependent tunneling device includes an electrically insulative material intermediate layer, a magnetization reference layer on one of the opposite major surfaces of the intermediate layer, and a memory film of a magnetostrictive, anisotropic ferromagnetic material on the other of the opposite major surfaces of the intermediate layer. The memory film material has a magnetization directed at an angle with respect to the relatively fixed direction of the magnetization reference layer, due to an effective magnetic bias field being present, in a first kind of stress condition with unequal coercivities for external magnetic fields applied in opposite directions. In one kind of stress condition the device has a coercivity with a magnitude exceeding that of the effective magnetic bias field, and in another kind of stress condition, the device has a coercivity with a magnitude less than that of the effective magnetic bias field.

摘要翻译： 自旋相关隧道装置包括电绝缘材料中间层，在中间层的相对主表面之一上的磁化参考层，以及磁致伸缩各向异性铁磁材料的记录膜，位于相对的主表面上 中间层。 存储膜材料由于存在有效的磁偏置场而具有相对于磁化参考层的相对固定方向成一定角度的磁化，在第一类应力条件下，对于施加在外部磁场的不同的矫顽力 相反的方向 在一种应力条件下，器件具有超过有效磁偏置场的矫顽力，在另一种应力条件下，该器件的矫顽力的幅度小于有效磁偏置场的矫顽力。

公开(公告)号：US20150070979A1

公开(公告)日：2015-03-12

申请号：US14072537

申请日：2013-11-05

申请人： QUALCOMM Incorporated

发明人： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC分类号： G11C11/16

CPC分类号： G11C11/1695 ,  G09C1/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

摘要： One feature pertains to a method of implementing a physically unclonable function. The method includes initializing an array of magnetoresistive random-access memory (MRAM) cells to a first logical state, where each of the MRAM cells have a random transition voltage that is greater than a first voltage and less than a second voltage. The transition voltage represents a voltage level that causes the MRAM cells to transition from the first logical state to a second logical state. The method further includes applying a programming signal voltage to each of the MRAM cells of the array to cause at least a portion of the MRAM cells of the array to randomly change state from the first logical state to the second logical state, where the programming signal voltage is greater than the first voltage and less than the second voltage.

摘要翻译： 一个特征涉及实现物理上不可克隆功能的方法。 该方法包括将磁阻随机存取存储器（MRAM）单元的阵列初始化为第一逻辑状态，其中每个MRAM单元具有大于第一电压且小于第二电压的随机转变电压。 转换电压表示使MRAM单元从第一逻辑状态转换到第二逻辑状态的电压电平。 该方法还包括将编程信号电压施加到阵列的每个MRAM单元，以使阵列的MRAM单元的至少一部分随机地将状态从第一逻辑状态改变到第二逻辑状态，其中编程信号 电压大于第一电压且小于第二电压。

公开(公告)号：US20150055410A1

公开(公告)日：2015-02-26

申请号：US13153471

申请日：2011-06-06

申请人： Krishnakumar Mani

发明人： Krishnakumar Mani

IPC分类号： G11C11/14

CPC分类号： G11C11/14 ,  G11C7/14 ,  G11C7/24 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1695 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

摘要： Memory circuit and method for at least partially dissipating an external magnetic field before the magnetic field affects operation of an array of addressable magnetic storage element stacks in the memory circuit. Multiple dummy magnetic storage element stacks are provided around the periphery of the array. Each of the dummy stacks is substantially circular for orienting along the external magnetic field, thereby causing the dissipation. Each of the addressable and the dummy stacks may be formed with a magnetic tunnel junction (MTJ).

摘要翻译： 用于在磁场影响存储器电路中的可寻址磁存储元件堆阵列的操作之前至少部分耗散外部磁场的存储器电路和方法。 围绕阵列周边设置多个虚拟磁存储元件堆叠。 每个虚拟堆叠基本上是圆形的，用于沿着外部磁场定向，从而导致耗散。 可寻址和虚拟堆叠中的每一个可以形成有磁性隧道结（MTJ）。

公开(公告)号：US20140286085A1

公开(公告)日：2014-09-25

申请号：US13966151

申请日：2013-08-13

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Tadashi MIYAKAWA

IPC分类号： G11C11/16 ,  H02H3/20

CPC分类号： G11C11/1695 ,  G11C5/147 ,  H02H3/20 ,  H02H9/046

摘要： According to one embodiment, a power supply circuit includes a first circuit connected to a first line, to which a power supply voltage is applied, and a second line, and a power supply clamp circuit connected to the first and second lines. The power supply clamp circuit includes a current path circuit which connects the first and the second lines to each other, and a control circuit which outputs a control signal to the current path circuit. The current path circuit includes a transistor and a diode group. The power supply clamp circuit is driven during a period in which a first voltage is applied to the first line and controls a potential of the first line so as to become a potential lower than the first voltage.

摘要翻译： 根据一个实施例，电源电路包括连接到施加电源电压的第一线路的第一电路和第二线路，以及连接到第一和第二线路的电源钳位电路。 电源钳位电路包括将第一和第二线路相互连接的电流路径电路，以及向电流路径电路输出控制信号的控制电路。 电流路径电路包括晶体管和二极管组。 电源钳位电路在向第一线路施加第一电压并且控制第一线路的电位以便变为低于第一电压的电位的时段内被驱动。