公开(公告)号：US06490203B1

公开(公告)日：2002-12-03

申请号：US09863697

申请日：2001-05-24

申请人： Yuan Tang

发明人： Yuan Tang

IPC分类号： G11C1604

CPC分类号： G11C16/345 ,  G11C16/28 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459

摘要： There is provided a reading circuit and method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells. A fixed control gate bias voltage is applied to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current. Varied control gate bias voltages are applied to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations. In a second embodiment, the different reference currents are generated from a current source.

摘要翻译： 提供了一种用于在闪存EEPROM存储器核心单元阵列中的选定的存储器核心单元上执行程序验证，擦除验证和过擦除校正验证模式的读取电路和方法。 将固定的控制栅极偏置电压施加到其状态将被验证以产生核心单元漏极电流的核心单元晶体管的控制栅极。 各种控制栅极偏置电压被施加到单个参考单元晶体管的控制栅极，用于产生对应于预定操作模式的不同参考电流。 在第二实施例中，从电流源产生不同的参考电流。

公开(公告)号：US20020176281A1

公开(公告)日：2002-11-28

申请号：US09863697

申请日：2001-05-24

发明人： Yuan Tang

IPC分类号： G11C016/06

CPC分类号： G11C16/345 ,  G11C16/28 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459

摘要： There is provided a reading circuit and method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells. A fixed control gate bias voltage is applied to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current. Varied control gate bias voltages are applied to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations. In a second embodiment, the different reference currents are generated from a current source.

摘要翻译： 提供了一种用于在闪存EEPROM存储器核心单元阵列中的选定的存储器核心单元上执行程序验证，擦除验证和过擦除校正验证模式的读取电路和方法。 将固定的控制栅极偏置电压施加到其状态将被验证以产生核心单元漏极电流的核心单元晶体管的控制栅极。 各种控制栅极偏置电压被施加到单个参考单元晶体管的控制栅极，用于产生对应于预定操作模式的不同参考电流。 在第二实施例中，从电流源产生不同的参考电流。

公开(公告)号：US06404680B1

公开(公告)日：2002-06-11

申请号：US09468933

申请日：1999-12-22

申请人： Oh Won Kwon

发明人： Oh Won Kwon

IPC分类号： G11C1604

CPC分类号： G11C29/789 ,  G11C16/04 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/345 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004

摘要： The present invention comprises a first means to select all repair fuse cells, using a test mode, and to sense each repair fuse cell state depending on the applied read-out voltage; a logical means to generate decision signals to decide the overerasing state of said repair fuse cells by logically combining sensed signals from said each repair fuse cell; and a second means to read output signals of said logical means.

摘要翻译： 本发明包括使用测试模式选择所有修理保险丝单元并根据所应用的读出电压感测每个修复熔丝单元状态的第一装置; 通过逻辑地组合来自所述每个修复熔丝单元的感测信号，产生决定信号以决定所述修复熔丝单元的过度曝光状态的逻辑装置; 以及读取所述逻辑装置的输出信号的第二装置。

公开(公告)号：US06208560B1

公开(公告)日：2001-03-27

申请号：US09599397

申请日：2000-06-22

申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

IPC分类号： G11C1606

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

摘要： A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20 V is applied to the control gate of any selected one of the memory cells, 0 V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11 V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

摘要翻译： 包括串联连接的多个存储单元的NAND单元单元。 对所有存储单元进行擦除操作。 然后，对所有存储单元施加与施加在擦除操作中的擦除电压极性相反的软编程电压，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到存储单元中的任何一个存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到 剩余存储单元的控制门。 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

公开(公告)号：US5689459A

公开(公告)日：1997-11-18

申请号：US744559

申请日：1996-11-05

申请人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

发明人： Shang-De Chang ,  Jia-Hwang Chang ,  Edwin Chow

IPC分类号： G11C16/04 ,  G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： G11C16/345 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/115 ,  H01L29/7883

摘要： A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

公开(公告)号：US5650962A

公开(公告)日：1997-07-22

申请号：US586243

申请日：1996-01-16

申请人： Kenshiro Arase

发明人： Kenshiro Arase

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/10 ,  G11C16/34 ,  G11C29/00 ,  G11C29/12 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/345 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3409

摘要： A semiconductor nonvolatile memory device which is able to be repeatedly rewritten a certain number of times by electrically erasing its memory cells, the semiconductor nonvolatile memory device being comprised of a detecting circuit for detecting if there are any memory cells which had been over-erased (mal-erased) at each rewrite operation, a write circuit for writing, into any cell where over-erasure had been detected, data of a normal or inverted level based on the data which should be written in the over-erased cells, and a recorder for recording if the write circuit wrote the data the same or inverted in level.

摘要翻译： 一种半导体非易失性存储器件，其能够通过电擦除其存储单元而被重复重写一定次数，所述半导体非易失性存储器件包括检测电路，用于检测是否存在已经被擦除的任何存储器单元 在每次重写操作时，写入电路用于写入到已被检测到过度擦除的任何单元中，基于应该写入过去被擦除的单元的数据的正常或反相电平的数据，以及 如果写入电路将数据写入相同或倒置的级别，则用于记录。

公开(公告)号：US20170229187A1

公开(公告)日：2017-08-10

申请号：US15494134

申请日：2017-04-21

申请人： Proton World International N.V.

发明人： Ronny Van Keer ,  Youssef Ahssini

IPC分类号： G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/20

CPC分类号： G11C16/349 ,  G06F12/0246 ,  G11C16/14 ,  G11C16/20 ,  G11C16/26 ,  G11C16/345

摘要： A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the flash memory each time the counter is incremented/decremented.

公开(公告)号：US09728268B1

公开(公告)日：2017-08-08

申请号：US15264075

申请日：2016-09-13

申请人： Kabushiki Kaisha Toshiba

发明人： Kazutaka Takizawa ,  Masaaki Niijima

IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C8/10 ,  G11C16/16

CPC分类号： G11C16/3445 ,  G11C8/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/345 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028

摘要： According to one embodiment, a memory device includes a controller, and a nonvolatile memory controlled by the controller, the nonvolatile memory executing an erase operation by an algorithm which repeats loops, each loop including an erase step applying an erase pulse to a memory cell and a verify step verifying a threshold voltage of the memory cell after the erase step, an erase-verify-read voltage using the verify step changing in a x-th loop (x is a natural number equal to or larger than 2). The controller is capable of changing a value of x, and indicates the value of x to the nonvolatile memory.

公开(公告)号：US20170148519A1

公开(公告)日：2017-05-25

申请号：US15365575

申请日：2016-11-30

申请人： Integrated Silicon Solution, Inc.

发明人： Kyoung Chon Jin

IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  H01L29/788 ,  H01L27/11524 ,  H01L27/11529 ,  H01L23/528 ,  G11C16/04 ,  G11C16/30

CPC分类号： G11C16/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30 ,  G11C16/345 ,  G11C16/3459 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/7884

摘要： A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCl). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption

公开(公告)号：US20170125107A1

公开(公告)日：2017-05-04

申请号：US15093935

申请日：2016-04-08

申请人： SK hynix Inc.

发明人： Yong Hwan HONG ,  Byung Ryul KIM

IPC分类号： G11C16/16 ,  G11C16/10 ,  G11C16/08

CPC分类号： G11C16/16 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3409 ,  G11C16/345

摘要： There are provided a storage device, a memory system having the same, and an operating method thereof. A storage device includes a plurality of memory blocks for storing data, a peripheral circuit for selecting multiple memory blocks from among the plurality of memory blocks and simultaneously performing an erase operation on the multiple memory blocks, and a control circuit for controlling the peripheral circuit so that the multiple memory blocks are simultaneously erased, and an erase operation and an erase verification operation of a selected memory block from among the multiple memory blocks are performed.