公开(公告)号：US09812212B2

公开(公告)日：2017-11-07

申请号：US15408434

申请日：2017-01-18

申请人： eMemory Technology Inc.

发明人： Hsueh-Wei Chen ,  Wei-Ren Chen ,  Wein-Town Sun

IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C16/14 ,  H01L27/11519

CPC分类号： H01L27/11558 ,  G11C7/065 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C8/10 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42328

摘要： A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.

公开(公告)号：US09812176B2

公开(公告)日：2017-11-07

申请号：US15364291

申请日：2016-11-30

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Shih-Hung Chen

IPC分类号： G11C5/02 ,  G11C16/10 ,  G11C5/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565

CPC分类号： G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C16/10 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565

摘要： A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer≧2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=⅕ to ½. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines. M array regions of the N array regions are configured to operate simultaneously. M is an integer. M/N=½ or 1.

公开(公告)号：US09799396B2

公开(公告)日：2017-10-24

申请号：US15367829

申请日：2016-12-02

申请人： Renesas Electronics Corporation

发明人： Shinji Tanaka ,  Makoto Yabuuchi ,  Yuta Yoshida

IPC分类号： G11C5/06 ,  G11C11/419 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C7/08 ,  G11C7/22 ,  G11C11/418

CPC分类号： G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

摘要： A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

公开(公告)号：US20170301389A1

公开(公告)日：2017-10-19

申请号：US15429021

申请日：2017-02-09

申请人： Micron Technology, Inc.

发明人： Kazuhiko Kajigaya

IPC分类号： G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G06F13/16

CPC分类号： G11C11/4076 ,  G06F13/161 ,  G11C5/025 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/107

摘要： Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a sub word line selection signal decoder which activates at least one of a plurality of sub word selection signals responsive to row address signals; a column segment selection signal decoder which activates at least one of a plurality of column segment signals responsive to a portion of column address signals and a portion of the row address signals; a column segment selection circuit which activates at least one of a plurality of column-subword selection signals responsive to the activated column segment signal and the activated sub word selection signal; and a sub word line driver which activates at least one of a plurality of sub word lines responsive to an activated main word line and the activated sub word selection signal.

公开(公告)号：US09792970B2

公开(公告)日：2017-10-17

申请号：US15405509

申请日：2017-01-13

申请人： SK hynix Inc.

发明人： Cheol Hoe Kim ,  Kyeong Tae Kim

IPC分类号： G11C8/12 ,  G11C8/18

CPC分类号： G11C8/18 ,  G11C5/147 ,  G11C8/10 ,  G11C8/12

摘要： A semiconductor system includes a first semiconductor device configured to output command addresses; and a second semiconductor device configured to generate a first control signal including a pulse controlled in its pulse width in synchronization with a toggling time of a bank active signal for selecting a bank to be activated in an active operation in response to the command addresses, a second control signal enabled in response to the bank active signal, and an internal voltage in response to the first and second control signals.

公开(公告)号：US09786366B2

公开(公告)日：2017-10-10

申请号：US15197539

申请日：2016-06-29

申请人： MICRON TECHNOLOGY, INC.

发明人： Stephen H. Tang

IPC分类号： G11C8/00 ,  G11C13/00 ,  G11C8/08 ,  G11C8/10

CPC分类号： G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069

摘要： Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.

公开(公告)号：US20170243623A1

公开(公告)日：2017-08-24

申请号：US15048133

申请日：2016-02-19

申请人： Micron Technology, Inc.

发明人： Graham Kirsch ,  Martin Steadman

IPC分类号： G11C8/10 ,  G11C8/06

CPC分类号： G11C8/10 ,  G11C8/06

摘要： Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.

公开(公告)号：US09742408B1

公开(公告)日：2017-08-22

申请号：US15274322

申请日：2016-09-23

申请人： International Business Machines

发明人： Paul Alan Bunce ,  Yuen Hung Chan ,  John D Davis ,  Antonio Raffaele Pelella

IPC分类号： H03K19/096 ,  G11C8/10

CPC分类号： H03K19/0963 ,  G11C8/10 ,  G11C8/18

摘要： A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

公开(公告)号：US09741400B2

公开(公告)日：2017-08-22

申请号：US15341707

申请日：2016-11-02

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Shuhei Nagatsuka ,  Tomokazu Yokoi ,  Naoaki Tsutsui ,  Kazuaki Ohshima ,  Tatsuya Onuki

IPC分类号： G11C7/10 ,  G11C7/06 ,  H01L27/11582 ,  H01L27/11568 ,  G11C5/06 ,  G11C8/10 ,  G11C7/12

CPC分类号： G11C7/065 ,  G11C5/063 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/30 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582

摘要： A semiconductor device or a memory device with a reduced area, a large storage capacity, a high-speed operation, or low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, a first wiring, a second wiring, a sense amplifier circuit, a decoder, a step-up circuit, a level shifter, and a buffer circuit. The first wiring is electrically connected to the buffer circuit and a second gate electrode of the first transistor. The second wiring is electrically connected to the sense amplifier circuit and the drain electrode of the second transistor. The capacitor is electrically connected to the drain electrode of the first transistor and the source electrode of the second transistor.

公开(公告)号：US20170213594A1

公开(公告)日：2017-07-27

申请号：US15480419

申请日：2017-04-06

申请人： GSI Technology Inc.

发明人： Avidan Akerib ,  Eli Ehrman

IPC分类号： G11C15/04 ,  G06F9/30

CPC分类号： G11C15/04 ,  G06F9/3016 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/18 ,  G11C8/10

摘要： A computing device includes a memory array built of several sections having memory cells arranged in rows and column, at least one cell in each column of the memory array being connected to a bit line; and at least one multiplexer to connect a bit line in a first column of a first section to a bit line in a second column in a second section different from the first section, where the second column is not continuous with the first column; and a decoder to activate at least two word lines of the first section and a word line connected to a cell in the second column in the second section to write a bit line voltage associated with a result of a logical operation performed on the first column into the cell in the second column.