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    Semiconductor structure formation method and mask
    71.
    发明授权
    Semiconductor structure formation method and mask 有权

    公开(公告)号：US11810787B2

    公开(公告)日：2023-11-07

    申请号：US17218809

    申请日：2021-03-31

    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

    Inventor： Jisong Jin

    IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3215 ,  H01L21/3115

    CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/0332 ,  H01L21/31155 ,  H01L21/3215 ,  H01L21/32155

    Abstract: A semiconductor structure formation method and a mask are provided. One form of the formation method includes: providing a base, including a target layer; forming a mandrel material layer on the base, the mandrel material layer including a first region and a second region encircling the first region; performing ion doping on the mandrel material layer in the second region, the ion doping being suitable for increasing the etching resistance of the mandrel material layer, where the mandrel material layer in the second region serves as an anti-etching layer, and the mandrel material layer in the first region serves as a mandrel layer; forming a first trench that runs through, along a first direction, at least part of the mandrel material layer in the first region, where part of the mandrel material layer in the first region remains at two sides of the first trench along a second direction; forming spacers on side walls of the first trench, so that the spacers form a first groove by encircling; removing the mandrel layer to form second grooves; and etching, using the anti-etching layer and the spacers as masks, the target layer below the first groove and the second grooves, to form the target pattern. In embodiments and implementations of the present disclosure, a pitch between target patterns is further compressed.

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    76.
    发明公开
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230326741A1

    公开(公告)日：2023-10-12

    申请号：US18331924

    申请日：2023-06-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    Inventor： SHIH-WEI PENG ,  CHIA-TIEN WU ,  JIANN-TYNG TZENG

    IPC: H01L21/02 ,  H01L21/033

    CPC classification number: H01L21/02172 ,  H01L21/0337 ,  H01L23/585

    Abstract: A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell; forming a plurality of first metal strips on a first plane; forming a first trench over a boundary between the first cell and the second cell, wherein a bottom surface of the first trench is located on a second plane over the first plane; filling the first trench with a nonconductive material, resulting in a separating wall; and forming a plurality of second metal strips on a third plane over the second plane, wherein the plurality of second metal strips comprise a first second metal strip and a second second metal strip separated from each other by the separating wall.

    Self Aligned Multiple Patterning Method
    78.
    发明公开
    Self Aligned Multiple Patterning Method 审中-公开

    公开(公告)号：US20230290676A1

    公开(公告)日：2023-09-14

    申请号：US17989438

    申请日：2022-11-17

    Applicant: Tokyo Electron Limited

    Inventor： David Power ,  David Conklin ,  Jodi Grzeskowiak ,  Michael Murphy

    IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

    CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76897

    Abstract: A method of patterning a substrate, where the method includes: forming first structures over a memorization layer, the first structures including a first row of lines that are parallel with each other and spaced apart from each other; executing a first anti-spacer formation process to form first trenches along sidewalls of the first structures and sidewalls of a first fill material, the first trenches defining a first etch pattern; transferring the first etch pattern into the memorization layer and removing materials above the memorization layer; forming second structures over the memorization layer, the second structures including a second row of lines that are parallel with each other and spaced apart, placement of the second row of lines being shifted relative to the first row of lines; executing a second anti-spacer formation process to form second trenches formed along sidewalls of the second structures and sidewalls of a second fill material, the second trenches defining a second etch pattern; and transferring the second etch pattern into the memorization layer and removing materials above the memorization layer.

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