公开(公告)号：US20180358973A1

公开(公告)日：2018-12-13

申请号：US15950968

申请日：2018-04-11

Applicant: Renesas Electronics Corporation

Inventor： Yuichi MARUYAMA ,  Noriaki MATSUNO

IPC: H03L7/099 ,  H03K3/53 ,  H03L1/02

CPC classification number: H03L7/099 ,  H03B5/04 ,  H03B5/366 ,  H03B2200/005 ,  H03B2200/0068 ,  H03B2201/0266 ,  H03K3/53 ,  H03L1/026 ,  H03L1/027 ,  H03L1/028

Abstract: Increases of circuit scale and power consumption are suppressed while frequency deviation is kept within a predetermined allowable range. A semiconductor device according to an embodiment includes a variable load capacity circuit including a plurality of load capacity elements coupled in parallel to one end of a crystal resonator and a plurality of switches that are respectively serially coupled to the load capacity elements, and a switch control unit that controls ON/OFF of the switches on the basis of information to be an index of frequency deviation due to temperature change of a frequency signal obtained by oscillating the crystal resonator. The switch control unit changes the number of switches that will be turned ON among the plurality of switches so that an absolute value of the frequency deviation becomes small when the information is not included in a predetermined allowable range.

公开(公告)号：US09948281B2

公开(公告)日：2018-04-17

申请号：US15256453

申请日：2016-09-02

Applicant: Peregrine Semiconductor Corporation

Inventor： Tero Tapio Ranta

IPC: H03K3/00 ,  H03J3/16 ,  H03K17/687

CPC classification number: H03J3/16 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03J3/20 ,  H03J5/24 ,  H03K17/687

Abstract: Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

公开(公告)号：US20180097521A1

公开(公告)日：2018-04-05

申请号：US15676080

申请日：2017-08-14

Applicant: Apple Inc.

Inventor： Joachim S. Hammerschmidt ,  Robert G. Lorenz

IPC: H03L7/089 ,  H03C3/09 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18

CPC classification number: H03L7/0893 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/025 ,  H03B2201/0266 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0991 ,  H03J2200/10 ,  H03L7/0805 ,  H03L7/0996 ,  H03L7/104 ,  H03L7/105 ,  H03L7/18 ,  H03L7/189 ,  H03L2207/06

Abstract: A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

公开(公告)号：US20180069530A1

公开(公告)日：2018-03-08

申请号：US15256453

申请日：2016-09-02

Applicant: Peregrine Semiconductor Corporation

Inventor： Tero Tapio Ranta

IPC: H03J3/16 ,  H03K17/687

CPC classification number: H03J3/16 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03J3/20 ,  H03J5/24 ,  H03K17/687

Abstract: Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

公开(公告)号：US20170324378A1

公开(公告)日：2017-11-09

申请号：US15659322

申请日：2017-07-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mina SHAHMOHAMMADI ,  Masoud BABAIE ,  Robert Bogdan STASZEWSKI

IPC: H03B5/12

CPC classification number: H03B5/1243 ,  H03B5/1218 ,  H03B5/1228 ,  H03B5/1262 ,  H03B5/1296 ,  H03B2201/0266

Abstract: The embodiments of the invention relate to a radio frequency oscillator, the radio frequency oscillator comprising a resonator circuit resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.

公开(公告)号：US09667193B2

公开(公告)日：2017-05-30

申请号：US14447478

申请日：2014-07-30

Applicant: Texas Instruments Incorporated

Inventor： Sudipto Chakraborty

IPC: H03K3/16 ,  H03B5/12 ,  H03B5/08 ,  H03B1/00

CPC classification number: H03B5/1215 ,  H03B1/00 ,  H03B5/08 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/125 ,  H03B5/1262 ,  H03B5/1296 ,  H03B2200/0082 ,  H03B2201/0266

Abstract: A wide tuning range oscillator system uses multiple active cores with cross-coupled transistors and multiple tapped inductors having windings that can be connected to circuit nodes. These active cores are connected to a pair of symmetric tapping points and are switched ON/OFF by biasing elements. Biasing schemes and the topology of the individual cross-coupled cores may be different from each other. The tapping points are symmetrically arranged around the center point of the inductor. One or more of the active cores may be enabled for tuning the center frequency of the oscillator system.

公开(公告)号：US20160241187A1

公开(公告)日：2016-08-18

申请号：US14622626

申请日：2015-02-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chang Lin ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Tien-Chun Yang

IPC: H03B5/12

CPC classification number: H03B5/1262 ,  H03B1/00 ,  H03B5/1228 ,  H03B2201/0266 ,  H03L7/095 ,  H03L7/099

Abstract: A circuit includes at least two LC voltage controlled oscillators (LCVCOs). Each LCVCO includes a switch to selectively turn on or off the LCVCO. One selected LCVCO of the at least two LCVCOs is configured to provide a differential LCVCO output. A converter coupled to the at least two LCVCOs is configured to receive the differential LCVCO output and provide an output signal with a full voltage swing.

Abstract translation: 一个电路包括至少两个LC压控振荡器（LCVCO）。 每个LCVCO都包括有选择地打开或关闭LCVCO的开关。 所选择的至少两个LCVCO的LCVCO被配置为提供差分LCVCO输出。 耦合到所述至少两个LCVCO的A转换器被配置为接收差分LCVCO输出并且提供具有全电压摆幅的输出信号。

公开(公告)号：US09112448B2

公开(公告)日：2015-08-18

申请号：US14065240

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Emmanouil Terrovitis

IPC: H03B5/36

CPC classification number: H03B5/362 ,  H03B5/364 ,  H03B2200/0046 ,  H03B2200/005 ,  H03B2200/0052 ,  H03B2200/0082 ,  H03B2201/0266

Abstract: An oscillator circuit may selectively switch between a normal mode and a low-power mode in response to a mode signal. During the normal mode, the oscillator circuit may employ a first amplifier configuration and a first capacitive loading to generate a high-accuracy clock signal having a relatively low frequency error. During the low power mode, the oscillator circuit may employ a second amplifier configuration and a second capacitive loading to generate a low-power clock signal using minimal power consumption. A compensation circuit may be used to offset a relatively high frequency error during the low-power mode.

Abstract translation: 响应于模式信号，振荡器电路可以选择性地在正常模式和低功率模式之间切换。 在正常模式期间，振荡器电路可以采用第一放大器配置和第一容性负载来产生具有相对较低频率误差的高精度时钟信号。 在低功率模式期间，振荡器电路可采用第二放大器配置和第二容性负载，以使用最小功耗生成低功率时钟信号。 补偿电路可以用于在低功率模式期间抵消相对较高的频率误差。

公开(公告)号：US20150116051A1

公开(公告)日：2015-04-30

申请号：US14065240

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Emmanouil Terrovitis

IPC: H03H9/24

CPC classification number: H03B5/362 ,  H03B5/364 ,  H03B2200/0046 ,  H03B2200/005 ,  H03B2200/0052 ,  H03B2200/0082 ,  H03B2201/0266

Abstract: An oscillator circuit may selectively switch between a normal mode and a low-power mode in response to a mode signal. During the normal mode, the oscillator circuit may employ a first amplifier configuration and a first capacitive loading to generate a high-accuracy clock signal having a relatively low frequency error. During the low power mode, the oscillator circuit may employ a second amplifier configuration and a second capacitive loading to generate a low-power clock signal using minimal power consumption. A compensation circuit may be used to offset a relatively high frequency error during the low-power mode.

Abstract translation: 响应于模式信号，振荡器电路可以选择性地在正常模式和低功率模式之间切换。 在正常模式期间，振荡器电路可以采用第一放大器配置和第一容性负载来产生具有相对较低频率误差的高精度时钟信号。 在低功率模式期间，振荡器电路可采用第二放大器配置和第二容性负载，以使用最小功耗生成低功率时钟信号。 补偿电路可以用于在低功率模式期间抵消相对较高的频率误差。

公开(公告)号：US08963648B2

公开(公告)日：2015-02-24

申请号：US13598426

申请日：2012-08-29

Applicant: Hyman Shanan

Inventor： Hyman Shanan

IPC: H03B5/12 ,  H03B1/04

CPC classification number: H03B1/04 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/005 ,  H03B2200/0062 ,  H03B2200/009 ,  H03B2201/0258 ,  H03B2201/0266 ,  H03B2202/03

Abstract: Apparatus and methods are also disclosed related to an oscillator that includes a switching network configured to tune a resonant frequency of a resonant circuit. One such apparatus includes a switching network having a circuit element, such as a capacitor, that can be selectively coupled to the resonant circuit by a switch, such as a field effect transistor. For instance, the switch can electrically couple to circuit element to the resonant circuit when on and not electrically couple the circuit element to the resonant circuit when off. An active circuit can assert a high impedance on an intermediate node between the switch and the circuit element when the switch is off.

Abstract translation: 还公开了一种与振荡器相关的装置和方法，该振荡器包括配置成调谐谐振电路的谐振频率的开关网络。 一种这样的设备包括具有诸如电容器的电路元件的开关网络，其可以通过诸如场效应晶体管的开关选择性地耦合到谐振电路。 例如，当断开时，开关可以在接通时将电路元件电耦合到谐振电路，而不将电路元件电耦合到谐振电路。 当开关关闭时，有源电路可以在开关和电路元件之间的中间节点上断言高阻抗。