公开(公告)号：US20150316975A1

公开(公告)日：2015-11-05

申请号：US14798050

申请日：2015-07-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Jared L. Zerbe ,  Brian S. Leibowitz

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/324 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2213/0038 ,  G11C5/14 ,  G11C5/148 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254

Abstract: A memory controller is transitioned to a low-power mode in which an active-mode resource required to transmit memory access commands to a memory device at a first command-signaling frequency is disabled. The memory controller transmits a first memory access command to the memory device using an alternative signaling resource during a transitional interval in which the active-mode resource is re-enabled.

Abstract translation: 存储器控制器转换到低功率模式，其中禁用以第一命令信令频率将存储器访问命令发送到存储器设备所需的主动模式资源。 存储器控制器在其中重新启用活动模式资源的过渡间隔期间使用替代信令资源向存储器设备发送第一存储器访问命令。

公开(公告)号：US20150286408A1

公开(公告)日：2015-10-08

申请号：US14745746

申请日：2015-06-22

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Richard E. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

IPC: G06F3/06

CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Abstract translation: 存储器组件包括包含动态随机存取存储器（DRAM）存储单元的存储器核心和用于接收外部命令的第一电路。 外部命令包括指定发送从存储器核心访问的数据的读取命令。 存储器组件还包括响应于读取命令和在校准期间可操作以提供至少第一数据模式和第二数据模式的读取命令和模式寄存器电路将数据发送到外部总线的第二电路。 在校准期间，第一数据模式和第二数据模式中的所选择的一个被响应于在校准期间接收到的读命令，被第二电路发送到外部总线上。 此外，响应于在校准期间接收到的写入命令，第一和第二数据模式中的至少一个被写入模式寄存器电路。

公开(公告)号：US20150248327A1

公开(公告)日：2015-09-03

申请号：US14631570

申请日：2015-02-25

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1048 ,  G11C5/04 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

Abstract translation: 公开了一种存储器模块。 存储器模块包括衬底以及相应的第一，第二和第三存储器件。 第一存储器件是第一类型，其设置在衬底上并且具有可寻址的存储位置。 第二存储器件也是第一类型，并且包括专用于存储与第一存储器件中的不良存储位置相关联的故障地址信息的存储单元。 第三存储器件是第一类型的，并且包括专用于替换为存储位置不良的存储单元的存储单元。

公开(公告)号：US09111587B2

公开(公告)日：2015-08-18

申请号：US14319544

申请日：2014-06-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Paul D. Franzon

IPC: G11C7/00 ,  G11C5/02 ,  G11C29/00 ,  H01L23/538

CPC classification number: G11C5/02 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/80 ,  G11C29/808 ,  G11C2213/71 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.

Abstract translation: 公开了一种堆叠存储器，其包括具有第一存储位置的第一集成电路存储器芯片和与第一集成电路存储器芯片堆叠关系地设置的第二集成电路存储器芯片。 第二集成电路存储器芯片具有第二存储位置。 提供了冗余存储器，其包括专用于存储第一或第二集成电路存储器芯片中的故障地址位置的故障地址信息的第一存储区域。 冗余存储器包括专用于存储对应于故障地址位置的数据的第二存储区域。 匹配逻辑将输入的数据传输地址与存储的故障地址信息进行匹配。

公开(公告)号：US09110596B2

公开(公告)日：2015-08-18

申请号：US14445516

申请日：2014-07-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Jared L. Zerbe ,  Brian S. Leibowitz

IPC: G11C7/22 ,  G06F3/06 ,  G11C11/4072 ,  G11C11/4076 ,  G06F1/32 ,  G11C5/14

CPC classification number: G06F1/3275 ,  G06F1/324 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2213/0038 ,  G11C5/14 ,  G11C5/148 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254

Abstract: A memory device is transitioned to a low-power mode in which an active-mode resource required to receive memory access commands from a memory controller at a first command-signaling frequency of the memory device is disabled. A first memory access command, transmitted by the memory controller, is received within the memory device using an alternative signaling resource during a transitional interval in which the active-mode resource is re-enabled.

Abstract translation: 存储器件被转换到低功率模式，其中禁用在存储器设备的第一命令信号频率处从存储器控制器接收存储器访问命令所需的活动模式资源。 由存储器控制器发送的第一存储器访问命令在其中重新启用活动模式资源的过渡间隔期间使用备用信令资源在存储器设备内被接收。

公开(公告)号：US20150229468A1

公开(公告)日：2015-08-13

申请号：US14695597

申请日：2015-04-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L7/00

CPC classification number: H04L7/0016 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract translation: 方法和系统提供在通信信道的正常操作期间不时地执行校准周期。 校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。 使用第二组件上的接收器从通信链路接收校准模式。 响应于所接收的校准模式来确定通信信道的参数的校准值。 校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。 对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，并将这些校准模式重新发送回第一组件，以用于调整第一组件上的通道的参数。

公开(公告)号：US20150227188A1

公开(公告)日：2015-08-13

申请号：US14694046

申请日：2015-04-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract translation: 存储器系统的存储器控​​制器组件将存储器访问请求存储在事务队列中，直到被服务，使得随着时间的推移，事务队列在被占用和空状态之间交替。 响应于检测到事务队列已经保持在空状态达预定时间，存储器控制器将存储器系统转换到低功率模式。 在向低功率模式的转变中，存储器控制器禁用在一个或多个附加存储器件的同步通信电路内对时间数据信号操作所需的一个或多个定时信号的振荡，并且还禁用同步通信中的一个或多个功耗电路 一个或多个存储器件的电路。

公开(公告)号：US20150223333A1

公开(公告)日：2015-08-06

申请号：US14687687

申请日：2015-04-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: H05K1/11

CPC classification number: H05K1/11 ,  G06F1/184 ,  G06F13/1694 ,  G06F13/4068 ,  G06F15/7803 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4082 ,  G11C11/4093 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a motherboard substrate includes first and second sets of data lines, the first set of data lines arranged into a first set of nibbles and the second set of data lines are arranged into a second set of nibbles with each of the first and the second sets of nibbles including a respective timing line for a respective timing signal. The motherboard substrate also includes a processor socket connected to the first set of data lines, a first slot connected to the processor socket via a first subset of the first set of nibbles, and a second slot connected to the processor socket via a second subset of the first set of nibbles and connected to the first slot via the second set of nibbles.

Abstract translation: 这里描述的实施例描述了用于存储器系统的技术。 主板基板的一个实现包括第一和第二组数据线，布置成第一组半字节的第一组数据线和第二组数据线被布置成第二组半字节，其中第一和第 第二组半字节包括用于相应定时信号的相应定时线。 主板基板还包括连接到第一组数据线的处理器插座，经由第一组半字节的第一子集连接到处理器插座的第一插槽，以及经由第二组子集 第一组半字节，并通过第二组半字节连接到第一个插槽。

公开(公告)号：US20150212953A1

公开(公告)日：2015-07-30

申请号：US14683080

申请日：2015-04-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/16 ,  G11C7/10 ,  G11C5/02

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/02 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract translation: 半导体存储器系统包括第一半导体存储器管芯和第二半导体存储器管芯。 第一半导体存储器管芯包括主数据接口，用于在写操作期间接收输入数据流，并将输入数据流反序列化为第一多个数据流，并且还包括耦合到主数据接口的辅数据接口， 发送第一多个数据流。 第二半导体存储器管芯包括耦合到第一半导体存储器管芯的次级数据接口的次级数据接口，以接收第一多个数据流。

公开(公告)号：US20150187412A1

公开(公告)日：2015-07-02

申请号：US14613282

申请日：2015-02-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G11C11/406

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1636 ,  G06F13/1689 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4061

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

Abstract translation: 一种系统包括存储器控制器和具有命令接口和多个存储器组的存储器件，每个存储体具有多行存储器单元。 存储器控制器向存储器件发送自动刷新命令。 响应于自动刷新命令，在第一时间间隔期间，存储器件执行刷新操作以刷新存储器单元，并且存储器件的命令接口在第一时间间隔的持续时间内被置于校准模式。 同时，在第一时间间隔的至少一部分期间，存储器控制器执行存储器件的命令接口的校准。 自动刷新命令可以指定要刷新存储器件的存储体的顺序，使得存储器件以指定的存储体顺序顺序地刷新多个存储体中的相应行。