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    Stacked memory with redundancy
    851.
    发明授权
    Stacked memory with redundancy 有权
    堆叠内存冗余

    公开(公告)号：US08804394B2

    公开(公告)日：2014-08-12

    申请号：US13728330

    申请日：2012-12-27

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Paul D. Franzon

    IPC: G11C5/02

    CPC classification number: G11C5/02 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/80 ,  G11C29/808 ,  G11C2213/71 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path.

    Abstract translation: 公开了一种堆叠式存储器，其包括具有第一存储位置并与第二集成电路存储器芯片堆叠的第一集成电路存储器芯片。 冗余存储器由第一和第二集成电路存储器芯片共享，并且具有选择性地替换第一或第二集成电路存储器芯片中的相应存储位置的冗余存储位置。 堆叠式存储器还包括用于耦合到外部集成电路存储器控制器和相应的第一和第二信号路径的引脚接口。 第一信号路径通过第一和第二集成电路存储器芯片形成，并且耦合到冗余存储器和引脚接口。 第二信号路径通过第一和第二集成电路存储器芯片形成，并且经由第一信号路径耦合到冗余存储器和引脚接口。

    Memory Systems and Methods for Dynamically Phase Adjusting a Write Strobe and Data to Account for Receive-Clock Drift
    853.
    发明申请
    Memory Systems and Methods for Dynamically Phase Adjusting a Write Strobe and Data to Account for Receive-Clock Drift 有权
    用于动态相位调整写入频闪和数据以记录接收时钟漂移的存储器系统和方法

    公开(公告)号：US20140181393A1

    公开(公告)日：2014-06-26

    申请号：US14047118

    申请日：2013-10-07

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G11C11/406

    CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/40615 ,  G11C11/409 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

    Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

    Abstract translation: 存储器系统包括将数据写入存储器件并从存储器件读取数据的存储器控​​制器。 伴随写入数据的写入数据选通信号在写入数据有效时向存储器件指示，而伴随着来自存储器件的数据的读取选通器在读取数据有效时向存储器控制器指示。 存储器控制器自适应地控制写入数据选通的相位以补偿存储器件的定时漂移。 存储器控制器使用读取信号作为漂移的度量。

    Memory module having a write-timing calibration mode
    854.
    发明授权
    Memory module having a write-timing calibration mode 有权
    具有写定时校准模式的存储器模块

    公开(公告)号：US08743636B2

    公开(公告)日：2014-06-03

    申请号：US13890801

    申请日：2013-05-09

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G11C7/10 ,  G06F12/00

    CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

    Abstract: In memory module populated by memory components having a write-timing calibration mode, control information that specifies a write operation is received via an address/control signal path and write data corresponding to the write operation is received via a data signal path. Each memory component receives multiple delayed versions of a timing signal used to indicate that the write data is valid, and outputs signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay interval between outputting the control information on the address/control signal path and outputting the write data on the data signal path.

    Abstract translation: 在由具有写定时校准模式的存储器组件填充的存储器模块中，经由地址/控制信号路径接收指定写入操作的控制信息，并经由数据信号路径接收与写操作对应的写数据。 每个存储器组件接收用于指示写入数据有效的定时信号的多个延迟版本，并且输出与定时信号的多个延迟版本对应的信号，以使得能够在存储器控制器中确定输出 对地址/控制信号路径进行控制信息，并在数据信号路径上输出写入数据。

    Memory component with terminated and unterminated signaling inputs
    856.
    发明授权
    Memory component with terminated and unterminated signaling inputs 有权
    具有终止和未终止信号输入的存储器组件

    公开(公告)号：US08625371B2

    公开(公告)日：2014-01-07

    申请号：US13923634

    申请日：2013-06-21

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

    IPC: G11C7/00

    CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

    Abstract: A memory component has a signaling interface, data input/output (I/O) circuitry, command/address (CA) circuitry and clock generation circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input timed by a second clock signal, the CA signals indicating read and write operations to be performed within the memory component. The clock generation circuitry generates the first clock signal with a phase that establishes alignment between a leading edge of the bit time for each read data bit and a respective transition of the second clock signal.

    Abstract translation: 存储器组件具有信令接口，数据输入/输出（I / O）电路，命令/地址（CA）电路和时钟产生电路。 信令接口包括片上终端数据I / O和未终止的CA输入。 数据I / O电路专用于以由选通信号定时的数据I / O对写入数据位进行采样，并发送由第一时钟信号定时的读取数据位，每个写入和读取数据位对于位有效 时间在数据I / O。 CA电路在CA输入端采样CA信号，以第二时钟信号定时，CA信号指示要在存储器组件内执行的读和写操作。 时钟产生电路产生第一时钟信号，该相位在每个读取数据位的位时间的前沿和第二时钟信号的相应转换之间建立对齐。

    Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration
    857.
    发明申请
    Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration 有权
    具有模式寄存器电路的存储器组件，用于提供用于校准的数据模式

    公开(公告)号：US20130346685A1

    公开(公告)日：2013-12-26

    申请号：US13967245

    申请日：2013-08-14

    Applicant: Rambus Inc.

    Inventor： Craig E. Hampel ,  Richard S. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

    IPC: G06F12/02

    CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

    Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

    Abstract translation: 存储器组件包括包含动态随机存取存储器（DRAM）存储单元的存储器核心和用于接收外部命令的第一电路。 外部命令包括指定发送从存储器核心访问的数据的读取命令。 存储器组件还包括响应于读取命令和在校准期间可操作以提供至少第一数据模式和第二数据模式的读取命令和模式寄存器电路将数据发送到外部总线的第二电路。 在校准期间，第一数据模式和第二数据模式中的所选择的一个被响应于在校准期间接收到的读命令，被第二电路发送到外部总线上。 此外，响应于在校准期间接收到的写入命令，第一和第二数据模式中的至少一个被写入模式寄存器电路。

    STACKED MEMORY DEVICE WITH REDUNDANT RESOURCES TO CORRECT DEFECTS
    858.
    发明申请
    STACKED MEMORY DEVICE WITH REDUNDANT RESOURCES TO CORRECT DEFECTS 有权
    具有冗余资源的堆叠存储器件以纠正缺陷

    公开(公告)号：US20130279280A1

    公开(公告)日：2013-10-24

    申请号：US13865110

    申请日：2013-04-17

    Applicant: RAMBUS INC.

    Inventor： Paul Damian Franzon ,  Evan Lawrence Erickson ,  Thomas Vogelsang ,  Frederick A. Ware

    IPC: G11C29/04

    CPC classification number: G11C29/04 ,  G11C29/702 ,  G11C29/808

    Abstract: A memory device includes a stack of circuit layers, each circuit layer having formed thereon a memory circuit configured to store data and a redundant resources circuit configured to provide redundant circuitry to correct defective circuitry on at least one memory circuit formed on at least one layer in the stack. The redundant resources circuit includes a partial bank of redundant memory cells, wherein an aggregation of the partial bank of redundant memory cells in each of the circuit layers of the stack includes at least one full bank of redundant memory cells and wherein the redundant resources circuit is configured to replace at least one defective bank of memory cells formed on any of the circuit layers in the stack with at least a portion of the partial bank of redundant memory cells formed on any of the circuit layers in the stack.

    Abstract translation: 存储器件包括电路层堆叠，每个电路层上形成有存储器电路，其被配置为存储数据，冗余资源电路被配置为提供冗余电路以校正在至少一个层上形成的至少一个存储器电路上的有缺陷的电路 堆栈。 所述冗余资源电路包括冗余存储器单元的部分组，其中所述堆叠的每个电路层中的冗余存储器单元的部分组的聚集包括至少一个全部冗余存储器单元，并且其中所述冗余资源电路为 被配置为替换形成在堆叠中的任何电路层上的至少一个存储单元的至少一个有缺陷的存储单元组，其中所述冗余存储器单元的部分库的至少一部分形成在堆叠中的任何电路层上。

    Memory Component with Terminated and Unterminated Signaling Inputs
    859.
    发明申请
    Memory Component with Terminated and Unterminated Signaling Inputs 有权
    具有终止和未终止信令输入的存储器组件

    公开(公告)号：US20130279278A1

    公开(公告)日：2013-10-24

    申请号：US13923634

    申请日：2013-06-21

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

    IPC: G11C7/22

    CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

    Abstract: A memory component has a signaling interface, data input/output (I/O) circuitry, command/address (CA) circuitry and clock generation circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input timed by a second clock signal, the CA signals indicating read and write operations to be performed within the memory component. The clock generation circuitry generates the first clock signal with a phase that establishes alignment between a leading edge of the bit time for each read data bit and a respective transition of the second clock signal.

    Abstract translation: 存储器组件具有信令接口，数据输入/输出（I / O）电路，命令/地址（CA）电路和时钟产生电路。 信令接口包括片上终端数据I / O和未终止的CA输入。 数据I / O电路专用于以由选通信号定时的数据I / O对写入数据位进行采样，并发送由第一时钟信号定时的读取数据位，每个写入和读取数据位对于位有效 时间在数据I / O。 CA电路在CA输入端采样CA信号，以第二时钟信号定时，CA信号指示要在存储器组件内执行的读和写操作。 时钟产生电路产生第一时钟信号，该相位在每个读取数据位的位时间的前沿和第二时钟信号的相应转换之间建立对齐。

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