公开(公告)号：US20100109753A1

公开(公告)日：2010-05-06

申请号：US12605032

申请日：2009-10-23

Applicant: YUN-YOUNG LEE ,  Kyu-Chan Lee ,  Ho-Cheol Lee

Inventor： YUN-YOUNG LEE ,  Kyu-Chan Lee ,  Ho-Cheol Lee

IPC: H01L37/00

CPC classification number: G01K7/015 ,  G01K2219/00

Abstract: A method of outputting temperature data in a semiconductor device and a temperature data output circuit are provided. A pulse signal is generated in response to a booting enable signal activated in response to a power-up signal and the generation is inactivated in response to a mode setting signal during a power-up operation. A comparison signal is generated in response to the pulse signal by comparing a reference voltage independent of temperature with a sense voltage that varies with temperature change. The temperature data is changed in response to the comparison signal. Thus, the temperature data output circuit can rapidly output the exact temperature of the semiconductor device measured during the power-up operation.

Abstract translation: 提供了一种在半导体器件和温度数据输出电路中输出温度数据的方法。 响应于响应于上电信号而被激活的引导使能信号而产生脉冲信号，并且响应于上电操作期间的模式设置信号而使生成失效。 通过将与温度无关的参考电压与随温度变化而变化的感测电压进行比较，响应于脉冲信号产生比较信号。 响应于比较信号来改变温度数据。 因此，温度数据输出电路可以快速输出在上电操作期间测量的半导体器件的精确温度。

公开(公告)号：US07394711B2

公开(公告)日：2008-07-01

申请号：US11616846

申请日：2006-12-27

Applicant: Chi-Sung Oh ,  Ho-Cheol Lee ,  Nam-Jong Kim

Inventor： Chi-Sung Oh ,  Ho-Cheol Lee ,  Nam-Jong Kim

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/12 ,  G11C11/40603 ,  G11C11/40618

Abstract: A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.

Abstract translation: 提供一种半导体存储器件及其方法，用于根据外部命令和刷新模式改变访问共享存储区域的访问权限。 在一个实施例中，半导体存储器件包括用于输入用于第一或第二模式刷新操作的命令信号的多个输入/输出端口，被分成多个不同存储区域的存储器阵列，该存储器阵列包括至少可访问的共享存储器区域 多个输入/输出端口中的两个，以及用于响应于外部命令信号分配访问共享存储器区域的访问权限的授权控制块。 授权控制块还可以生成授权控制信号，用于优先地分配访问共享存储器区域的访问权限到输入/输出端口，以输入用于第一模式刷新操作的命令信号。

公开(公告)号：US20070297258A1

公开(公告)日：2007-12-27

申请号：US11612866

申请日：2006-12-19

Applicant: Kyung-Woo Nam ,  Ho-Cheol Lee

Inventor： Kyung-Woo Nam ,  Ho-Cheol Lee

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C11/406 ,  G11C7/1075 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618

Abstract: A semiconductor memory device and a self-refresh method in which the semiconductor memory device includes a plurality of input/output ports having respective independent operation, a period of self-refresh through one of the plurality of input/output ports being subordinate to a kind of operation through another input/output port. Whereby, a refresh characteristic in a multi-port semiconductor memory device including a dual-port semiconductor memory device may be improved.

Abstract translation: 一种半导体存储器件和自刷新方法，其中所述半导体存储器件包括具有各自独立操作的多个输入/输出端口，所述多个输入/输出端口中的一个输入/输出端口中的一个从属于一种类型的自刷新周期 的操作通过另一个输入/输出端口。 因此，可以提高包括双端口半导体存储器件的多端口半导体存储器件中的刷新特性。

公开(公告)号：US20050194664A1

公开(公告)日：2005-09-08

申请号：US11107897

申请日：2005-04-18

Applicant: Ho-Cheol Lee ,  Jae-Hoon Kim ,  Jung-Su Ryu

Inventor： Ho-Cheol Lee ,  Jae-Hoon Kim ,  Jung-Su Ryu

IPC: H01L21/60 ,  H01L23/50 ,  H01L23/495

CPC classification number: H01L24/06 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  Y10T29/49121 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A variety of pad arrangements are provided for semiconductor devices for reducing the likelihood of bonding failures, particularly those due to shorts, and/or for reducing the difference in length between bonding wires to decrease signal skew during operation of the semiconductor device and improve signal integrity.

公开(公告)号：US06172896B2

公开(公告)日：2001-01-09

申请号：US09351729

申请日：1999-07-12

Applicant: Ho-cheol Lee

Inventor： Ho-cheol Lee

IPC: G11C1700

CPC classification number: G11C17/16

Abstract: An integrated circuit device such as an integrated circuit memory device, includes a first fuse group such as a first laser fuse group including a plurality of first laser fuses each having a first narrow end, a second opposite end which is wider and a bent central portion. Pitches of the first end of the plurality of first laser fuses are narrow and pitches of the second end are wide. The plurality of first laser fuses are adjacent one another. A second fuse group such as a second laser fuse group includes a plurality of second laser fuses each having a first wide end, a second opposite end which is narrower, and a bent central portion. Pitches of the first end of the plurality of second laser fuses are wide and pitches of the second end are narrow. The second plurality of laser fuses are adjacent one another. The first ends of the laser fuses in the first laser fuse group are adjacent the first ends of laser fuses in the second laser fuse group. The second ends of the laser fuses in the first laser fuse group are adjacent the second ends of the laser fuses in the second laser fuse group. The central portions of the outer laser fuses of the first and second laser fuse groups are not bent, but straight. Accordingly, when a specific laser fuse is blown, neighboring laser fuses need not be damaged, and the density of the laser fuse area may be increased.

Abstract translation: 诸如集成电路存储器件的集成电路器件包括第一熔丝组，例如第一激光熔丝组，其包括多个第一激光熔丝，每个第一激光熔丝具有第一窄端，第二相对端较宽，弯曲的中心部 。 多个第一激光熔丝的第一端的间距窄，第二端的间距较宽。 多个第一激光熔丝彼此相邻。 诸如第二激光熔丝组的第二熔丝组包括多个第二激光熔丝，每个第二激光熔丝具有第一宽端，第二相对端较窄，以及弯曲的中心部。 多个第二激光熔丝的第一端的间距宽，第二端的间距窄。 第二组激光熔丝彼此相邻。 第一激光熔丝组中的激光熔丝的第一端与第二激光熔丝组中的激光熔丝的第一端相邻。 第一激光熔丝组中的激光熔丝的第二端与第二激光熔丝组中的激光熔丝的第二端相邻。 第一和第二激光熔丝组的外部激光熔丝的中心部分不弯曲，而是直的。 因此，当特定的激光熔丝被熔断时，不需要损坏相邻的激光熔丝，并且可以增加激光熔丝区域的密度。

公开(公告)号：US5838990A

公开(公告)日：1998-11-17

申请号：US905562

申请日：1997-08-04

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G06F9/00 ,  G06F13/16

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5835956A

公开(公告)日：1998-11-10

申请号：US822148

申请日：1997-03-17

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G06F13/16

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5808948A

公开(公告)日：1998-09-15

申请号：US769615

申请日：1996-12-18

Applicant: Chul-soo Kim ,  Ho-cheol Lee

Inventor： Chul-soo Kim ,  Ho-cheol Lee

IPC: G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/24 ,  G11C7/00

CPC classification number: G11C29/24

Abstract: There is provided a semiconductor memory device which does not require an additional input pad to apply a signal for discriminating between a normal cell and a redundant cell. The semicodnuctor memory device has (claim 1). Therefore, the normal cell array or the redundant cell array is sequentially selected and tested by using the same input pad to which the bank select bit is input, without an additional pad.

Abstract translation: 提供了半导体存储器件，其不需要额外的输入焊盘来施加用于区分正常单元和冗余单元的信号。 半导体存储器件具有（权利要求1）。 因此，通过使用输入存储体选择位的相同的输入焊盘，而没有附加的焊盘，顺序地选择和测试正常单元阵列或冗余单元阵列。

公开(公告)号：US5703828A

公开(公告)日：1997-12-30

申请号：US580622

申请日：1995-12-29

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5673225A

公开(公告)日：1997-09-30

申请号：US623772

申请日：1996-03-29

Applicant: Woo-Seop Jeong ,  Ho-Cheol Lee

Inventor： Woo-Seop Jeong ,  Ho-Cheol Lee

IPC: G11C11/407 ,  G11C5/14 ,  G11C8/08 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C8/08

Abstract: A word line voltage boosting circuit varies a word line output voltage according to variation of the number of the word lines to be activated. A boosting circuit boosts a word line voltage which has been precharged to a first level voltage to a second level voltage in response to an activation signal. A voltage adding circuit further boosts the word line voltage to a third voltage level by adding a predetermined voltage to the second level voltage if the number of the word lines to be activated increases. A driving circuit includes a bootstrap circuit for stably providing the boosted word line voltage to an output line.

Abstract translation: 字线电压升压电路根据要激活的字线数量的变化来改变字线输出电压。 升压电路响应于激活信号将已被预充电到第一电平电压的字线电压升高到第二电平电压。 如果要激活的字线数量增加，则通过将预定电压加到第二电平电压，电压相加电路进一步将字线电压升压到第三电压电平。 驱动电路包括用于将升压的字线电压稳定地提供给输出线的自举电路。