公开(公告)号：US06780796B2

公开(公告)日：2004-08-24

申请号：US10625015

申请日：2003-07-22

申请人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L21324

CPC分类号： H01L21/322 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02694 ,  Y10S438/933

摘要： A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of strained SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 20%, by molecular weight; implanting H2+ ions into the SiGe layer; irradiating the substrate and SiGe layer, to relax the SiGe layer; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.

公开(公告)号：US06703293B2

公开(公告)日：2004-03-09

申请号：US10194383

申请日：2002-07-11

申请人： Douglas J. Tweet ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Jong-Jan Lee

发明人： Douglas J. Tweet ,  Sheng Teng Hsu ,  Jer-shen Maa ,  Jong-Jan Lee

IPC分类号： H01L21265

CPC分类号： H01L21/02381 ,  C30B25/02 ,  C30B29/52 ,  C30B31/22 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02694 ,  Y10S438/933

摘要： A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; amorphizing the Si1−XGeX layer at a temperature greater than Tc to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

摘要翻译： 在硅衬底上制造Si1-XGeX膜的方法包括制备硅衬底; 在硅衬底上外延沉积形成Si1-XGeX / Si界面的Si1-XGeX层; 在大于Tc的温度下使Si1-XGeX层非晶化以形成无定形的梯度SiGe层; 并在约650℃至1100℃的温度下对该结构退火约十秒至六十分钟以使SiGe层重结晶。

公开(公告)号：US06664117B2

公开(公告)日：2003-12-16

申请号：US10256380

申请日：2002-09-26

申请人： Wei-Wei Zhuang ,  Sheng Teng Hsu ,  Jong-Jan Lee

发明人： Wei-Wei Zhuang ,  Sheng Teng Hsu ,  Jong-Jan Lee

IPC分类号： H01L2100

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  Y10S502/525

摘要： A method of forming a multi-layered, spin-coated perovskite thin film on a wafer includes preparing a perovskite precursor solution including mixing solid precursor material into acetic acid forming a mixed solution; heating the mixed solution in air for between about one hour to six hours; and filtering the solution when cooled; placing a wafer in a spin-coating mechanism; spinning the wafer at a speed of between about 500 rpm to 3500 rpm; injecting the precursor solution onto the wafer surface; baking the coated wafer at a temperature of between about 100° C. to 300° C.; annealing the coated wafer at a temperature of between about 400° C. to 650° C. in an oxygen atmosphere for between about two minutes to ten minutes; repeating the spinning, injecting, baking and annealing steps until a perovskite thin film of desired thickness is obtained; and annealing the perovskite thin film at a temperature of between about 500° C. to 750° C. in an oxygen atmosphere for between about ten minutes to two hours.

公开(公告)号：US5962884A

公开(公告)日：1999-10-05

申请号：US905380

申请日：1997-08-04

申请人： Sheng Teng Hsu ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Jong Jan Lee

IPC分类号： G11C11/22 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/115 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L21/84 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/11502 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/78391 ,  G11C11/223

摘要： A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate includes implanting doping impurities of a first type into the substrate to form a conductive channel of a first type, implanting doping impurities of a second type in the conductive channel of the first type to form a conductive channel well of a second type, implanting doping impurities of a third type in the conductive channel well of the second type to form a conductive channel of a third type for use as a gate junction region, implanting doping impurities of a fourth type in the conductive channel sub-well of the third type on either side of the gate junction region to form plural conductive channels of a fourth type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction region. A ferroelectric memory cell includes a silicon substrate of a first conductive type, a well structure of a second conductive type formed in the substrate, a structure of a third conductive type formed in the well structure, for use as a gate junction region. A source junction region and a drain junction region are located in the sub-well on either side of the gate junction region, doped to form conductive channels of a fourth type. A FEM gate unit overlays the conductive channel of the third type. An insulating layer overlays the junction regions, the FEM gate unit and the substrate. Suitable electrodes are connected to the various active regions in the memory cell.

摘要翻译： 在硅衬底上形成具有铁电存储（FEM）栅极单元的半导体结构的方法包括将第一类型的掺杂杂质注入到衬底中以形成第一类型的导电沟道，将第二类型的掺杂杂质注入到 所述第一类型的导电沟道形成第二类型的导电沟道阱，在所述第二类型的导电沟道阱中注入第三类型的掺杂杂质以形成用作栅极结区域的第三类型的导电沟道， 在栅极结区域的任一侧上在第三类型的导电通道子阱中注入第四类型的掺杂杂质以形成用作源极结区域和漏极结区域的第四类型的多个导电沟道; 以及在栅极结区域上沉积FEM栅极单元。 铁电存储单元包括第一导电类型的硅衬底，形成在衬底中的第二导电类型的阱结构，形成在阱结构中的第三导电类型的结构，用作栅极结区域。 源极结区域和漏极结区域位于栅极结区域的任一侧的子阱中，被掺杂以形成第四类型的导电沟道。 FEM门单元覆盖第三类导电通道。 绝缘层覆盖了连接区域，FEM栅极单元和衬底。 合适的电极连接到存储单元中的各种有源区。

公开(公告)号：US5910673A

公开(公告)日：1999-06-08

申请号：US984801

申请日：1997-12-04

申请人： Sheng Teng Hsu ,  Katsumasa Fujii ,  Hidechika Kawazoe ,  Jong Jan Lee

发明人： Sheng Teng Hsu ,  Katsumasa Fujii ,  Hidechika Kawazoe ,  Jong Jan Lee

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L23/62

CPC分类号： H01L27/0266 ,  Y10S438/981

摘要： A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

摘要翻译： 提供具有多电平栅氧化层的MOS晶体管用于ESD保护电路中。 在漏极附近的厚栅极氧化层确保晶体管具有相对较大的漏极到栅极击穿电压。 靠近源极的薄栅极氧化层允许栅极电压以快速的开关速度开启和关闭晶体管。 MOS晶体管多电平栅极氧化物层的厚部分由硅（LOCOS）工艺的局部氧化形成，而薄栅极层在单独的步骤中形成。 还提供了用于制造上述多电平栅极氧化物层MOS晶体管的ESD保护电路和方法。

公开(公告)号：US09099718B2

公开(公告)日：2015-08-04

申请号：US13752930

申请日：2013-01-29

申请人： Yuhao Lu ,  Hidayat Kisdarjono ,  Jong-Jan Lee ,  David Evans

发明人： Yuhao Lu ,  Hidayat Kisdarjono ,  Jong-Jan Lee ,  David Evans

IPC分类号： H01M8/02 ,  H01M4/136 ,  H02J7/00 ,  H01M4/58 ,  H01M10/054 ,  H01M10/0568 ,  H01M10/44

CPC分类号： H01M4/5825 ,  H01M4/136 ,  H01M4/58 ,  H01M4/625 ,  H01M10/054 ,  H01M10/0568 ,  H01M10/446 ,  H01M2004/028 ,  H02J7/0063 ,  H02J7/0068 ,  Y02E60/122

摘要： A transition metal hexacyanoferrate (TMH) cathode battery is provided. The battery has a AxMn[Fe(CN)6]y.zH2O cathode, where the A cations are either alkali or alkaline-earth cations, such as sodium or potassium, where x is in the range of 1 to 2, where y is in the range of 0.5 to 1, and where z is in the range of 0 to 3.5. The AxMn[Fe(CN)6]y.zH2O has a rhombohedral crystal structure with Mn2+/3+ and Fe2+3+ having the same reduction/oxidation potential. The battery also has an electrolyte, and anode made of an A metal, an A composite, or a material that can host A atoms. The battery has a single plateau charging curve, where a single plateau charging curve is defined as a constant charging voltage slope between 15% and 85% battery charge capacity. Fabrication methods are also provided.

摘要翻译： 提供了一种过渡金属六氰基铁酸盐（TMH）阴极电池。 电池具有AxMn [Fe（CN）6] y.zH 2 O阴极，其中A阳离子是碱金属或碱土金属阳离子，如钠或钾，其中x在1至2的范围内，其中y是 在0.5至1的范围内，其中z在0至3.5的范围内。 AxMn [Fe（CN）6] y.zH2O具有具有相同还原/氧化电位的Mn2 + / 3 +和Fe2 + 3 +的菱方晶体结构。 电池还具有电解质和由A金属，A复合材料或能够承载A原子的材料制成的阳极。 电池具有单个平台充电曲线，其中单个平台充电曲线被定义为电池充电容量的15％至85％之间的恒定充电电压斜率。 还提供制造方法。

公开(公告)号：US08956760B2

公开(公告)日：2015-02-17

申请号：US13523694

申请日：2012-06-14

申请人： Yuhao Lu ,  Jong-Jan Lee

发明人： Yuhao Lu ,  Jong-Jan Lee

IPC分类号： H01M4/136

CPC分类号： H01B1/122 ,  B82Y30/00 ,  H01M4/0404 ,  H01M4/133 ,  H01M4/587

摘要： A structure of intimately contacting carbon-hexacyanometallate is provided for forming a metal-ion battery electrode. Several methods are provided for forming the carbon-hexacyanometallate intimate contact. These methods include (1) adding conducting carbon during the synthesis of hexacyanometallate and forming the carbon-hexacyanometallate powder prior to forming the paste for electrode printing; (2) coating with conducting carbon after hexacyanometallate powder formation and prior to forming the paste for electrode printing; and (3) coating a layer of conducting carbon over the hexacyanometallate electrode.

摘要翻译： 为了形成金属离子电池电极，提供了紧密接触六氰基金属碳酸盐的结构。 提供几种形成碳六氰基金属酸盐紧密接触的方法。 这些方法包括（1）在合成六氰基金属盐酸盐期间加入导电碳，并在形成用于电极印刷的糊料之前形成碳 - 六金属金属酸盐粉末; （2）在六金属金属酸盐粉末形成之后，在形成用于电极印刷的糊料之前用导电碳涂覆; 和（3）在六氰基金属盐电极上涂覆一层导电碳。

公开(公告)号：US20140231832A1

公开(公告)日：2014-08-21

申请号：US13773414

申请日：2013-02-21

申请人： Jong-Jan Lee

发明人： Jong-Jan Lee

IPC分类号： H01L27/15 ,  H01L33/42

CPC分类号： H01L23/552 ,  H01L27/15 ,  H01L27/156 ,  H01L33/42 ,  H01L33/48 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-terminal light emitting device (LED) chip, associated fabrication method, and LED array are provided. The method forms an n-doped semiconductor layer overlying a substrate, an active semiconductor layer overlying the n-doped semiconductor layer, and a p-doped semiconductor layer overlying the active semiconductor layer. A trench is formed through the p-doped and active semiconductor layers, exposing the n-doped semiconductor layer. In one aspect, the trench is formed at least part way, but not completely, through the n-doped semiconductor layer. Then, an LED P electrode is formed overlying a first region of the p-doped semiconductor layer, a diode P electrode is formed overlying a second region of the p-doped semiconductor layer that is separated from the first region of the p-doped semiconductor layer by the trench, and an N electrode is formed overlying a top surface of the exposed n-doped semiconductor layer in the trench, shared by the LED and diode.

摘要翻译： 提供三端子发光器件（LED）芯片，相关制造方法和LED阵列。 该方法形成覆盖衬底的n掺杂半导体层，覆盖n掺杂半导体层的有源半导体层和覆盖有源半导体层的p掺杂半导体层。 通过p掺杂和有源半导体层形成沟槽，暴露n掺杂半导体层。 在一个方面中，通过n掺杂半导体层至少部分地形成沟槽，但不完全形成沟槽。 然后，在p掺杂半导体层的第一区域上形成LED P电极，形成二极管P电极，覆盖从p掺杂半导体层的第一区域分离的p掺杂半导体层的第二区域 并且N沟道电极被形成在由LED和二极管共享的沟槽中的暴露的n掺杂半导体层的顶表面上。

公开(公告)号：US20140134791A1

公开(公告)日：2014-05-15

申请号：US13674005

申请日：2012-11-10

申请人： Sean Andrew VAIL ,  Alexey KOPOSOV ,  Jong-Jan LEE

发明人： Sean Andrew VAIL ,  Alexey KOPOSOV ,  Jong-Jan LEE

IPC分类号： H01L21/02

CPC分类号： H01L31/0326 ,  B82Y30/00 ,  B82Y40/00 ,  C09D11/00 ,  C09D11/005 ,  C09D11/54 ,  H01L21/02425 ,  H01L21/02568 ,  H01L21/02601 ,  H01L21/02614 ,  H01L21/02628 ,  H01L31/0322 ,  Y02E10/541

摘要： A method is provided for forming a solution-processed metal and mixed-metal selenide semiconductor using selenium (Se) nanoparticles (NPs). The method forms a first solution including SeNPs dispersed in a solvent. Added to the first solution is a second solution including a first material set of metal salts, metal complexes, or combinations thereof, which are dissolved in a solvent, forming a third solution. The third solution is deposited on a conductive substrate, forming a first intermediate film comprising metal precursors, from corresponding members of the first material set, and embedded SeNPs. As a result of thermally annealing, the metal precursors are transformed and the first intermediate film is selenized, forming a first metal selenide-containing semiconductor. In one aspect, the first solution further comprises ligands for the stabilization of SeNPs, which are liberated during thermal annealing. In another aspect, the metal selenide-containing semiconductor comprises copper, indium, gallium diselenide (CIGS).

摘要翻译： 提供了使用硒（Se）纳米颗粒（NP）形成溶液处理金属和混合金属硒化物半导体的方法。 该方法形成包含分散在溶剂中的SeNP的第一溶液。 添加到第一溶液中是第二溶液，其包括溶解在溶剂中的第一组金属盐，金属络合物或其组合，形成第三溶液。 第三溶液沉积在导电基底上，形成包含金属前体的第一中间膜，来自第一材料组的相应构件和嵌入的SeNP。 作为热退火的结果，金属前体被转化并且第一中间膜被硒化，形成第一含金属硒化物的半导体。 在一个方面，第一溶液还包含用于稳定SeNP的配体，其在热退火期间释放。 另一方面，含金属硒化物的半导体包括铜，铟，二硒化镓（CIGS）。

公开(公告)号：US20140037999A1

公开(公告)日：2014-02-06

申请号：US13564015

申请日：2012-08-01

申请人： Yuhao Lu ,  Sean Andrew Vail ,  Gregory M. Stecker ,  Jong-Jan Lee

发明人： Yuhao Lu ,  Sean Andrew Vail ,  Gregory M. Stecker ,  Jong-Jan Lee

IPC分类号： H01M4/36 ,  H01M2/38

CPC分类号： H01M12/08 ,  H01M2/40 ,  H01M4/58 ,  H01M8/04276 ,  H01M10/399 ,  Y02E60/128 ,  Y02E60/50

摘要： A battery is provided with an associated method for transporting metal-ions in the battery using a low temperature molten salt (LTMS). The battery comprises an anode, a cathode formed from a LTMS having a liquid phase at a temperature of less than 150° C., a current collector submerged in the LTMS, and a metal-ion permeable separator interposed between the LTMS and the anode. The method transports metal-ions from the separator to the current collector in response to the LTMS acting simultaneously as a cathode and an electrolyte. More explicitly, metal-ions are transported from the separator to the current collector by creating a liquid flow of LTMS interacting with the current collector and separator.

摘要翻译： 电池具有使用低温熔融盐（LTMS）在电池中输送金属离子的相关方法。 电池包括阳极，由LTMS形成的阴极，其温度低于150℃时具有液相，浸没在LTMS中的集电体以及介于LTMS和阳极之间的金属离子可渗透隔板。 响应于同时作为阴极和电解质的LTMS，该方法将金属离子从分离器输送到集电器。 更明确地说，通过产生与集电器和分离器相互作用的LTMS的液体流，将金属离子从分离器输送到集电器。