公开(公告)号：US20230412169A1

公开(公告)日：2023-12-21

申请号：US18331381

申请日：2023-06-08

Applicant: Renesas Electronics Corporation

Inventor： Koji TAKAYANAGI

IPC: H03K17/56

CPC classification number: H03K17/56

Abstract: A first P-type transistor and a second P-type transistor are connected in series between a power supply terminal and an output terminal. A first N-type transistor and a second N-type transistor are connected between a ground terminal and a power supply terminal. The second N-type transistor and the second P-type transistor are complementarily turned on and off in accordance with an input signal. A gate voltage control circuit changes at least one of the gate voltage of the P-type transistor whose drain is electrically connected to the output terminal and the gate voltage of the N-type transistor by following the output voltage VOUT of the output terminal while keeping the P-type transistor or the N-type transistor on-states.

公开(公告)号：US20230402494A1

公开(公告)日：2023-12-14

申请号：US18194802

申请日：2023-04-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuhito SHIRAISHI

IPC: H01L29/00 ,  H01C7/00 ,  H01L21/768 ,  H01L23/522 ,  H01C17/12

CPC classification number: H01L28/24 ,  H01C7/006 ,  H01L21/76877 ,  H01L23/5228 ,  H01C17/12 ,  H01L21/76843

Abstract: A semiconductor device includes a wiring layer, a dielectric layer covering the wiring layer, a thin film resistor provided on the dielectric layer, and a plug electrode connecting the thin film resistor to the wiring layer. The plug electrode includes a barrier layer and a buried layer. The buried layer is configured by the filling portion filling a region surrounded by a first incline surface, and an extension portion extending from the filling portion along a second incline surface. The thin film resistor is in contact with the filling portion and the extension portion of the plug electrode. A second incline angle between the second incline surface and a main surface of a semiconductor substrate is smaller than a first incline angle between the first incline surface and the main surface of the semiconductor substrate.

公开(公告)号：US20230402081A1

公开(公告)日：2023-12-14

申请号：US18313684

申请日：2023-05-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi TAKEDA

IPC: G11C11/16 ,  G11C5/08 ,  G11C7/06

CPC classification number: G11C11/1697 ,  G11C5/08 ,  G11C7/06

Abstract: A semiconductor device capable of increasing readout margin in a nonvolatile resistive random access memory is provided. A clamping circuit applies fixed potential to each of a memory element and a reference resistive element. A pre-charge circuit pre-charges first and second nodes to power-source potential. A sense amplifier amplifies the potential difference between the potential of the first node and the potential of the second node generated after a discharge period based on cell current and reference current after pre-charging made by the pre-charge circuit. A third node is coupled to the first and second nodes through a capacitor. An electric-charge supply circuit is connected to the third node, and supplies electric charge to the third node in the discharge period.

公开(公告)号：US11838393B2

公开(公告)日：2023-12-05

申请号：US17242609

申请日：2021-04-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Christian Mardmoeller ,  Dnyaneshwar Kulkarni ,  Thorsten Hoffleit

IPC: H04L29/06 ,  H04L69/08 ,  H04L69/18 ,  H04L45/741 ,  H04L12/66 ,  H04L69/325 ,  H04L45/302

CPC classification number: H04L69/08 ,  H04L12/66 ,  H04L45/741 ,  H04L69/18 ,  H04L45/306 ,  H04L69/325

Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.

公开(公告)号：US20230387924A1

公开(公告)日：2023-11-30

申请号：US18307475

申请日：2023-04-26

Applicant: Renesas Electronics Corporation

Inventor： Yusuke IMANAKA ,  Atsushi MOTOZAWA

IPC: H03L7/099 ,  H03L7/197

CPC classification number: H03L7/0998 ,  H03L7/1974

Abstract: A semiconductor device includes a phase interpolation circuit including an N-bit current digital-analog conversion circuit, a switch circuit, a capacitive element, an inverter, and a control logic circuit. The control logic circuit detects an end of a phase interpolation operation by using an output result of the inverter and outputs a first control signal for turning off the current digital-analog conversion circuit. Also, the control logic circuit detects the end of the phase interpolation operation by using the output result of the inverter and outputs a second control signal for turning off the inverter.

公开(公告)号：US20230387901A1

公开(公告)日：2023-11-30

申请号：US18303960

申请日：2023-04-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki OOTANI

IPC: H03K5/131 ,  G06F11/16

CPC classification number: H03K5/131 ,  G06F11/1641 ,  G06F11/1695

Abstract: A technique for enhancing reliability is provided. A semiconductor device includes a main device which operates in a delayed lockstep mode, a sub device which operates in parallel to the main device in a delayed lockstep mode, a delay circuit which delays an output of the main device, a switching circuit which switches the main device to the sub device according to failure information of the main device.

公开(公告)号：US20230376334A1

公开(公告)日：2023-11-23

申请号：US17748725

申请日：2022-05-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masahiro HASEGAWA

IPC: G06F9/455 ,  G06F12/0802

CPC classification number: G06F9/45558 ,  G06F12/0802 ,  G06F2009/45583

Abstract: A semiconductor device includes a plurality of processors capable of executing a plurality of virtual machines and a cache memory. Each of the plurality of virtual machines executes a different operating system from each other. A hypervisor sets allocation information so as to allocate ways of the cache memory which can be used by the virtual machine. When outputting a memory access request, each of the processors outputs virtual machine identification in association with the information memory access request. When the memory access request is not a cache hit, the cache memory selects a way to be replaced data based on the virtual machine identification information and the allocation information.

公开(公告)号：US20230376058A1

公开(公告)日：2023-11-23

申请号：US17748770

申请日：2022-05-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yusuke AIHARA ,  Kuniyasu TAJIMA ,  Naoyuki HAMANISHI ,  Tadashi KAMEYAMA

IPC: G05F1/46 ,  H01P3/08 ,  H01L23/66

CPC classification number: G05F1/46 ,  H01P3/081 ,  H01L23/66 ,  H01L2223/6627

Abstract: A semiconductor device includes a receiving terminal for receiving a signal transmitted through a signal transmission line, a reference plane voltage terminal connected to a refence plane as a refence for the signal on the signal transmission line and a voltage generating circuit configured to generate a refence plane voltage to be supplied to the reference plane voltage terminal based on the signal received by the receiving terminal.

公开(公告)号：US11824113B2

公开(公告)日：2023-11-21

申请号：US17901416

申请日：2022-09-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Machiko Sato ,  Akihiro Shimomura

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/1095 ,  H01L29/66734

Abstract: A semiconductor device has an impurity region covering a bottom of a gate trench and a column region. A bottom of the column region is deeper than a bottom of the gate trench. The impurity region is arranged between the gate trench and the column region. This structure can improve the characteristics of the semiconductor device.

公开(公告)号：US20230369178A1

公开(公告)日：2023-11-16

申请号：US18170159

申请日：2023-02-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshiyuki HATA

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/49513 ,  H01L24/08 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L23/49816 ,  H01L2924/182 ,  H01L2224/08055 ,  H01L2224/08113 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/4814 ,  H01L2224/4903

Abstract: A package construction includes: a die pad, and a suspension lead remaining portion connected to the die pad. Here, an offset portion is provided from a peripheral edge portion of the die pad to the suspension lead remaining portion. Also, the suspension lead remaining portion has: a first end portion connected to the die pad, and a second end portion opposite the first end portion. Further, the second end portion of the suspension lead remaining portion is exposed from the side surface of the sealing body at a position spaced apart from each of the upper surface and the lower surface.