公开(公告)号：US20230125262A1

公开(公告)日：2023-04-27

申请号：US17963065

申请日：2022-10-10

申请人： Rambus Inc.

发明人： Mark D. KELLAM ,  Dongyun LEE ,  Thomas VOGELSANG ,  Steven C. WOO

IPC分类号： G02B6/293 ,  G02B6/12 ,  H04B10/50

摘要： Command/address and timing information is distributed to buffer integrated circuits on a module using multiple wavelengths of light modulated with the same information. Each individual wavelength of modulated light carrying command/address information is received by a corresponding single buffer device that deserializes the command/address information and communicates it electrically to memory devices(s). Likewise, each individual wavelength of modulated light carrying timing/synchronization/clock information is received by a corresponding single buffer device and used to synchronize accesses to the memory device(s). Thus, multiple buffer integrated circuits on a module each receive information from the CPU using different wavelengths of light transmitted on the same waveguide.

公开(公告)号：US11630788B2

公开(公告)日：2023-04-18

申请号：US16921061

申请日：2020-07-06

申请人： Rambus Inc.

发明人： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC分类号： G06F13/16 ,  G11C7/22 ,  G06F1/10 ,  G06F1/06 ,  G06F1/08 ,  G06F1/04 ,  G11C7/04 ,  H04L7/033

摘要： A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US11625346B2

公开(公告)日：2023-04-11

申请号：US17715379

申请日：2022-04-07

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Kenneth L. Wright

IPC分类号： G06F11/00 ,  G06F13/16 ,  G06F11/07 ,  G06F13/40 ,  G06F11/20 ,  G06F11/16 ,  G06F11/10

摘要： Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

公开(公告)号：US11621030B2

公开(公告)日：2023-04-04

申请号：US17568656

申请日：2022-01-04

申请人： Rambus Inc.

发明人： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC分类号： G11C11/34 ,  G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

摘要： In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US20230101128A1

公开(公告)日：2023-03-30

申请号：US17954086

申请日：2022-09-27

申请人： Rambus Inc.

发明人： Frederick A. Ware

IPC分类号： G11C7/10 ,  G11C8/18

摘要： Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory controller is disclosed. The IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second command/address (C/A) interface transmits third and fourth read commands for third and fourth read data to a second memory C/A interface of a second bank group of memory. Receiver circuitry receives the first and second read data via a first data link interface and the third and fourth read data via the second data link interface. For a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and at a first serialization ratio. For a second operating mode, the first and second read data are received after respective second and third delays following transmission of the first and second read commands. The second and third delays are different from the first delays and from each other. The first and second data are received at a second serialization ratio that is different than the first serialization ratio.

公开(公告)号：US20230100348A1

公开(公告)日：2023-03-30

申请号：US17945616

申请日：2022-09-15

申请人： Rambus Inc.

发明人： Ian Shaeffer ,  Frederick A. Ware

IPC分类号： G06F12/14 ,  G06F3/06 ,  G06F13/16 ,  G06F12/02

摘要： A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

公开(公告)号：US11615037B2

公开(公告)日：2023-03-28

申请号：US17306410

申请日：2021-05-03

申请人： Rambus Inc.

发明人： Aws Shallal ,  Larry Grant Giddens

IPC分类号： G06F13/16 ,  G06F13/42

摘要： A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

公开(公告)号：US11609870B2

公开(公告)日：2023-03-21

申请号：US17296532

申请日：2019-11-21

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Christopher Haywood

IPC分类号： G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  G11C5/04 ,  G11C11/4093 ,  G11C11/4096

摘要： In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

公开(公告)号：US20230080033A1

公开(公告)日：2023-03-16

申请号：US17898800

申请日：2022-08-30

申请人： Rambus Inc.

发明人： Cosmin Iorga

IPC分类号： H03K3/0232 ,  H03K19/17784 ,  H03L7/099 ,  H03L7/195 ,  H03L7/081

摘要： Described is an integrated circuit with a driving amplifier that transmits a signal over a link (e.g. a wire) by raising and lowering a voltage on the link. A reference oscillator provides an error measure for the rate at which the voltage transitions between voltages, the slew rate. Slew-rate calibration circuitry adjusts the driving amplifier responsive to the error measure.

公开(公告)号：US20230072394A1

公开(公告)日：2023-03-09

申请号：US17897439

申请日：2022-08-29

申请人： Rambus Inc.

发明人： Christopher Haywood ,  Steven C. Woo

IPC分类号： G11C7/10

摘要： A memory system includes a memory controller, a plurality of serial data buffers, and a plurality of memory devices. The memory controller issues packetized commands and data to the serial data buffers. The serial data buffers each apply a different remapping function to remap an input command address in the packetized commands to respective remapped memory addresses that are different for each serial data buffer. The serial data buffers then issue commands to the memory devices using the remapped addresses. The remapping functions may be designed to mitigate row hammer effects. The serial data buffers may furthermore apply transformations to read and write data to facilitate encryption and decryption.