公开(公告)号：US20120039120A1

公开(公告)日：2012-02-16

申请号：US13157344

申请日：2011-06-10

申请人： Chi-Weon YOON ,  Dong-Hyuk CHAE ,  Sang-Wan NAM ,  Sung-Won YUN

发明人： Chi-Weon YOON ,  Dong-Hyuk CHAE ,  Sang-Wan NAM ,  Sung-Won YUN

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3418

摘要： A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer.

摘要翻译： 一种非易失性存储器件包括存储单元阵列，该存储单元阵列包括连接到相应的字线和连接到相应位线的列的行中的存储单元，存储程序数据的页缓冲器，用于编程和重新编程的读写电路 将程序数据写入到存储单元阵列的选择的存储单元中，并从编程的存储器单元中读取存储的数据;以及控制电路，其控制页面缓冲器和读写电路，以通过从其中加载程序数据对所选存储单元进行编程 页面缓冲区，并通过重新加载页面缓冲区中的程序数据来重新编程所选择的存储单元。

公开(公告)号：US20080112229A1

公开(公告)日：2008-05-15

申请号：US11563746

申请日：2006-11-28

申请人： Ji-ho Cho ,  Sang-Wan Nam

发明人： Ji-ho Cho ,  Sang-Wan Nam

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C11/34

CPC分类号： G11C16/24 ,  G11C7/067 ,  G11C7/12 ,  G11C16/26

摘要： A sense amplifier of a flash memory device maintains a bit line precharge level before a memory cell is sensed. The sense amplifier maintains the voltage of a bias signal sufficiently high using a second precharging circuit in a precharging operation to stably maintain the bit line precharge level set by a first precharging circuit. Accordingly, the sense amplifier can correctly sense an OFF cell using the stabilized bit line precharge voltage. Related methods and memory devices are also disclosed.

摘要翻译： 闪速存储器件的读出放大器在感测存储器单元之前保持位线预充电电平。 读出放大器在预充电操作中使用第二预充电电路来保持偏置信号的电压足够高以稳定地维持由第一预充电电路设置的位线预充电电平。 因此，读出放大器可以使用稳定的位线预充电电压来正确地感测OFF单元。 还公开了相关方法和存储器件。

公开(公告)号：US07372747B2

公开(公告)日：2008-05-13

申请号：US11482447

申请日：2006-07-07

申请人： Sang-Wan Nam ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Dae-Han Kim

IPC分类号： G11C5/14

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/12

摘要： A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for generating a plurality of constant voltages to be applied to the memory cell array, and a selection circuit for selecting one constant voltage among the plurality of the constant voltages and applying the selected one constant voltage to the memory cell array. The voltage generating circuit discharges a leakage current input by the selection circuit through a voltage division path, which generates the constant voltages.

摘要翻译： 一种闪存器件及其电压产生电路。 闪存包括配置有多个存储单元的存储单元阵列，用于产生施加到存储单元阵列的多个恒定电压的电压产生电路，以及用于选择多个存储单元中的一个恒定电压的选择电路 将所选择的一个恒定电压施加到存储单元阵列。 电压产生电路通过分压路径对由选择电路输入的漏电流进行放电，产生恒定电压。

公开(公告)号：US20070201277A1

公开(公告)日：2007-08-30

申请号：US11789624

申请日：2007-04-25

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

公开(公告)号：US20060215449A1

公开(公告)日：2006-09-28

申请号：US11263716

申请日：2005-11-01

申请人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

发明人： Sang-Wan Nam ,  Young-Ho Lim ,  Dae-Han Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/26

摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

摘要翻译： 在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑 电路。 感测放大电路串行地检测存储在多电平单元中的多个数据位。 提供数据缓冲器以缓冲由读出放大器检测到的数据位。 数据锁存电路一次存储数据缓冲器的输出值。 控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。 这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。 根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

公开(公告)号：US20060092716A1

公开(公告)日：2006-05-04

申请号：US11153508

申请日：2005-06-15

申请人： Sang-Wan Nam ,  Seung-Keun Lee

发明人： Sang-Wan Nam ,  Seung-Keun Lee

IPC分类号： G11C7/10

CPC分类号： G11C16/26 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106

摘要： A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The data latch circuit latches an output of the tri-state buffer. The data line connects the tri-state buffer and the data latch circuit. The memory device removes charge on the data line using a latch enable signal, which is applied to the tri-state buffer before a read operation.

摘要翻译： 存储器件包括读出放大器电路，三态缓冲器，数据锁存电路和数据线。 感测放大器电路感测并放大存储器单元的电流。 三态缓冲器接收读出放大器电路的输出。 数据锁存电路锁存三态缓冲器的输出。 数据线连接三态缓冲器和数据锁存电路。 存储器件使用锁存使能信号去除数据线上的电荷，该信号在读取操作之前被施加到三态缓冲器。

公开(公告)号：US10043583B2

公开(公告)日：2018-08-07

申请号：US15447357

申请日：2017-03-02

申请人： Sang-wan Nam ,  Dae-seok Byeon ,  Chi-weon Yoon

发明人： Sang-wan Nam ,  Dae-seok Byeon ,  Chi-weon Yoon

IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/16

摘要： Provided are a nonvolatile memory device and a method of performing a sensing operation on the nonvolatile memory device. The nonvolatile memory device includes a control logic coupled to a memory cell array including strings. The control logic is configured to control a first weak-on voltage applied to an unselected string selection line and a second weak-on voltage applied to an unselected ground selection line during a setup interval of the sensing operation for sensing data from a selected string. The unselected string selection line and ground selection line are connected to a string selection transistor and a ground selection transistor, respectively, of a same unselected string. The selected string and the unselected string are connected to a same bit line. The first weak-on voltage and second weak-on voltage are respectively less than a threshold voltage of the string selection transistor and the ground selection transistor in the unselected string.

公开(公告)号：US20180047449A1

公开(公告)日：2018-02-15

申请号：US15614671

申请日：2017-06-06

申请人： SANG-WAN NAM ,  SANG-IN PARK

发明人： SANG-WAN NAM ,  SANG-IN PARK

IPC分类号： G11C16/08 ,  G11C8/06 ,  G11C11/4099 ,  G11C16/34 ,  G11C11/408

CPC分类号： G11C16/08 ,  G11C8/06 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4099 ,  G11C16/10 ,  G11C16/34 ,  G11C16/3454 ,  G11C29/028 ,  H03K19/02

摘要： A nonvolatile memory device includes a memory cell array, a row decoder circuit, a page buffer circuit, and a control logic circuit. The control logic circuit controls the row decoder circuit and the page buffer circuit to perform: (1) a pre-program of sequentially selecting a plurality of memory blocks and increasing threshold voltages of string selection transistors or ground selection transistors of the selected memory block and (2) after the pre-program is completed, a main program of sequentially selecting the plurality of memory blocks, programming string selection transistors or ground selection transistors of the selected memory block, and performing a verification by using a verification voltage.

公开(公告)号：US09870825B2

公开(公告)日：2018-01-16

申请号：US14733239

申请日：2015-06-08

申请人： Sang-Wan Nam ,  Wandong Kim

发明人： Sang-Wan Nam ,  Wandong Kim

IPC分类号： G11C16/10 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04 ,  G11C11/56

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24

摘要： A nonvolatile memory device includes a memory cell array, an address decoder, a read & write circuit and control logic. The memory cell array includes a plurality of memory blocks including a plurality of cell strings, each cell string including a plurality of memory cells stacked in a direction perpendicular to a substrate. The control logic controls operations so that in a program operation, when the selected word line satisfies a precharge condition, a program voltage to be applied to the selected word line is applied before a pass voltage to be applied to an unselected word line.

公开(公告)号：US09666283B2

公开(公告)日：2017-05-30

申请号：US15152692

申请日：2016-05-12

申请人： Kyung-Hwa Kang ,  Sang-Wan Nam ,  Donghyuk Chae ,  ChiWeon Yoon

发明人： Kyung-Hwa Kang ,  Sang-Wan Nam ,  Donghyuk Chae ,  ChiWeon Yoon

IPC分类号： G11C16/04 ,  G11C16/08 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/24 ,  H01L23/528 ,  H01L27/11565

CPC分类号： G11C16/0483 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/24 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

摘要： Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.