公开(公告)号：US20090033308A1

公开(公告)日：2009-02-05

申请号：US12245360

申请日：2008-10-03

Applicant: Siva G. Narendra ,  James W. Tschanz ,  Vivek K. De ,  Stephen H. Tang

Inventor： Siva G. Narendra ,  James W. Tschanz ,  Vivek K. De ,  Stephen H. Tang

IPC: G05F5/00

CPC classification number: G06F1/206 ,  Y02D10/16

Abstract: A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.

Abstract translation: 系统可以包括获取表示提供给电气部件的过去电源电压的电源电压信息，基于电源电压信息获取表示电气部件的过去温度的温度信息和电气部件的性能特性的控制，以及 温度信息。 一些实施例还可以包括基于电源电压信息，温度信息以及电气部件的可靠性规格以及基于可靠性裕度的性能特性的改变来确定可靠性裕度。

公开(公告)号：US07403426B2

公开(公告)日：2008-07-22

申请号：US11137905

申请日：2005-05-25

Applicant: Fatih Hamzaoglu ,  Kevin Zhang ,  Nam Sung Kim ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De ,  Bo Zheng

Inventor： Fatih Hamzaoglu ,  Kevin Zhang ,  Nam Sung Kim ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek K. De ,  Bo Zheng

IPC: G11C11/34

CPC classification number: G11C5/14 ,  G11C11/413

Abstract: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.

Abstract translation: 在一些实施例中，存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。 可以公开和/或要求保护其他实施例。

公开(公告)号：US07385865B2

公开(公告)日：2008-06-10

申请号：US11001870

申请日：2004-12-01

Applicant: Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Gunjan H. Pandya ,  Vivek K. De

Inventor： Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Gunjan H. Pandya ,  Vivek K. De

IPC: G11C7/00 ,  G11C11/00

CPC classification number: G11C11/419

Abstract: In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.

Abstract translation: 在一个实施例中，提供了包括一个或多个列的存储器阵列，每个列包括被分成位单元组的多个位单元，每组比特单元可控制地耦合到单独的位线。

公开(公告)号：US07355246B2

公开(公告)日：2008-04-08

申请号：US11268430

申请日：2005-11-07

Applicant: Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

Inventor： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

IPC: H01L29/76

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

Abstract: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

Abstract translation: 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

公开(公告)号：US07321502B2

公开(公告)日：2008-01-22

申请号：US10956285

申请日：2004-09-30

Applicant: Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Alavi Mohsen ,  Vivek K. De

Inventor： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad M. Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen H. Tang ,  Alavi Mohsen ,  Vivek K. De

IPC: G11C17/00

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.

Abstract translation: 描述了一种在驱动电流通过电容器的同时在电容器的电介质材料内感应电介质击穿的方法。 电流特定于正在写入电容器的数据。 该方法还涉及通过解释由电容器电阻确定的电容器的行为来读取数据，其中电容器的电阻是诱导和驱动的结果。

公开(公告)号：US07288752B2

公开(公告)日：2007-10-30

申请号：US10620829

申请日：2003-07-16

Applicant: Ali Keshavarzi ,  Jaume A. Segura ,  Vivek K. De

Inventor： Ali Keshavarzi ,  Jaume A. Segura ,  Vivek K. De

IPC: G01J1/44 ,  H03K17/78

CPC classification number: G01T1/026 ,  H01L27/144

Abstract: A radiation measuring technique includes adjusting a threshold level of a radiation sensor in a radiation-measuring circuit and obtaining an output signal based on radiation dose sensed by the radiation sensor.

Abstract translation: 辐射测量技术包括调整辐射测量电路中的辐射传感器的阈值水平，并且基于由辐射传感器感测的辐射剂量获得输出信号。

公开(公告)号：US07282966B2

公开(公告)日：2007-10-16

申请号：US10953199

申请日：2004-09-28

Applicant: Siva G. Narendra ,  James W. Tschanz ,  Vivek K. De ,  Nasser A. Kurd ,  Javed Barkatullah

Inventor： Siva G. Narendra ,  James W. Tschanz ,  Vivek K. De ,  Nasser A. Kurd ,  Javed Barkatullah

IPC: H03K17/00

CPC classification number: G06F1/324 ,  G06F1/06 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126

Abstract: Apparatus and systems, as well as methods and articles, may operate to select a microprocessor clock frequency responsive to a desired voltage and/or a desired temperature of operation.

Abstract translation: 装置和系统以及方法和物品可以操作以响应于期望电压和/或期望的操作温度来选择微处理器时钟频率。

公开(公告)号：US07109776B2

公开(公告)日：2006-09-19

申请号：US10947869

申请日：2004-09-23

Applicant: James W. Tschanz ,  Dinesh Somasekhar ,  Vivek K. De

Inventor： James W. Tschanz ,  Dinesh Somasekhar ,  Vivek K. De

IPC: H03K3/013

CPC classification number: G06F1/10

Abstract: Some embodiments provide reception of a clock signal, reception of a gating signal, and output of a gated clock signal to a dual edge-triggered-clocked circuit. The gated clock signal is based on the clock signal and on the gating signal.

Abstract translation: 一些实施例提供时钟信号的接收，门控信号的接收以及门控时钟信号输出到双边沿触发时钟电路。 门控时钟信号基于时钟信号和门控信号。

公开(公告)号：US07098766B2

公开(公告)日：2006-08-29

申请号：US10760591

申请日：2004-01-21

Applicant: Donald S. Gardner ,  Peter Hazucha ,  Gerhard Schrom ,  Tanay Karnik ,  Vivek K. De

Inventor： Donald S. Gardner ,  Peter Hazucha ,  Gerhard Schrom ,  Tanay Karnik ,  Vivek K. De

IPC: H01F5/00

CPC classification number: H01F17/0006 ,  H01F10/132 ,  H01F10/187 ,  H01F10/265 ,  H01F2017/0053

Abstract: A transformer is provided that includes a plurality of metal lines and a magnetic material provided about the plurality of metal lines. The magnetic material may include a structure to reduce Eddy currents flowing in the magnetic material. This structure may be a plurality of slots extending perpendicular to the metal lines. This structure may also be a laminated structure.

Abstract translation: 提供一种变压器，其包括多个金属线和围绕多条金属线设置的磁性材料。 磁性材料可以包括减少在磁性材料中流动的涡流的结构。 该结构可以是垂直于金属线延伸的多个槽。 该结构也可以是层叠结构。

公开(公告)号：US07075180B2

公开(公告)日：2006-07-11

申请号：US10747805

申请日：2003-12-29

Applicant: Siva G. Narendra ,  James W. Tschanz ,  Victor Zia ,  Badarinath Kommandur ,  Vivek K. De

Inventor： Siva G. Narendra ,  James W. Tschanz ,  Victor Zia ,  Badarinath Kommandur ,  Vivek K. De

IPC: H01L23/10 ,  H01L23/34

CPC classification number: H01L23/367 ,  H01L23/50 ,  H01L24/31 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152

Abstract: In some embodiments, a method includes providing an integrated circuit (IC) die in a package. The IC die may have a metal layer on a back surface of the IC die. The method may also include applying a bias signal to the IC die via the metal layer.

Abstract translation: 在一些实施例中，一种方法包括在封装中提供集成电路（IC）裸片。 IC芯片可以在IC芯片的背面上具有金属层。 该方法还可以包括经由金属层向IC管芯施加偏置信号。