公开(公告)号：US20060128091A1

公开(公告)日：2006-06-15

申请号：US10905025

申请日：2004-12-10

申请人： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.

摘要翻译： 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个 第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

公开(公告)号：US20060057797A1

公开(公告)日：2006-03-16

申请号：US11266855

申请日：2005-11-04

申请人： Atul Ajmera ,  Andres Bryant ,  Percy Gilbert ,  Michael Gribelyuk ,  Edward Maciejewski ,  Renee Mo ,  Shreesh Narasimha

发明人： Atul Ajmera ,  Andres Bryant ,  Percy Gilbert ,  Michael Gribelyuk ,  Edward Maciejewski ,  Renee Mo ,  Shreesh Narasimha

IPC分类号： H01L21/8238

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

公开(公告)号：US06991979B2

公开(公告)日：2006-01-31

申请号：US10605311

申请日：2003-09-22

申请人： Atul C. Ajmera ,  Andres Bryant ,  Percy V. Gilbert ,  Michael A Gribelyuk ,  Edward P. Maciejewski ,  Renee T. Mo ,  Shreesh Narasimha

发明人： Atul C. Ajmera ,  Andres Bryant ,  Percy V. Gilbert ,  Michael A Gribelyuk ,  Edward P. Maciejewski ,  Renee T. Mo ,  Shreesh Narasimha

IPC分类号： H01L21/8238

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

公开(公告)号：US20050277263A1

公开(公告)日：2005-12-15

申请号：US10710001

申请日：2004-06-11

申请人： Renee Mo ,  Shreesh Narasimha

发明人： Renee Mo ,  Shreesh Narasimha

IPC分类号： H01L21/331 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76283

摘要： Shallow trench isolation structures are formed without CMP by depositing a thick pad nitride and depositing oxide trench fill material such that: a) the material in the trenches is above the silicon surface by a process margin that allows for removal of trench fill in subsequent front end steps so that the final trench fill level is substantially coplanar with the silicon; and b) the oxide on the interior walls is easily removed, so that the pad nitride is removed in a wet etch.

摘要翻译： 通过沉积厚衬垫氮化物和沉积氧化物沟槽填充材料形成浅沟槽隔离结构，使得：a）沟槽中的材料在硅表面之上，具有允许在随后的前端去除沟槽填充的工艺余量 使得最终沟槽填充水平基本上与硅共面; 和b）内壁上的氧化物容易去除，使得衬垫氮化物在湿蚀刻中被去除。

公开(公告)号：US09040399B2

公开(公告)日：2015-05-26

申请号：US13282619

申请日：2011-10-27

申请人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

发明人： MaryJane Brodsky ,  Ming Cai ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yue Liang ,  Liyang Song ,  Yanfeng Wang ,  Chun-Chen Yeh

IPC分类号： H01L21/425 ,  H01L29/66

CPC分类号： H01L29/66803

摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.

摘要翻译： 一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。 在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。 还公开了制造FinFET晶体管的方法。 还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

公开(公告)号：US08816473B2

公开(公告)日：2014-08-26

申请号：US13440172

申请日：2012-04-05

申请人： Arvind Kumar ,  Anthony I-Chih Chou ,  Renee T. Mo ,  Shreesh Narasimha

发明人： Arvind Kumar ,  Anthony I-Chih Chou ,  Renee T. Mo ,  Shreesh Narasimha

IPC分类号： H01L29/86 ,  H01L21/02

CPC分类号： H01L23/5256 ,  H01L21/84 ,  H01L28/20 ,  H01L29/86 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.

摘要翻译： 公开了提供精密电阻元件的半导体结构和制造方法。 多晶硅嵌入在硅衬底中。 可以掺杂多晶硅以控制电阻。 实施例可以包括电阻器，eFuse和绝缘体上硅结构。 一些实施例可以包括非矩形横截面。

公开(公告)号：US08803243B2

公开(公告)日：2014-08-12

申请号：US13342435

申请日：2012-01-03

申请人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

发明人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

IPC分类号： H01L21/70

CPC分类号： H01L21/823871 ,  H01L21/28079 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/4958

摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

摘要翻译： 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

公开(公告)号：US08455334B2

公开(公告)日：2013-06-04

申请号：US12631342

申请日：2009-12-04

申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L21/84

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66772

摘要： A method for forming an integrated circuit, the method includes forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate, and a SOI slab region that is disposed on the insulator substrate, and forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region.

摘要翻译： 一种用于形成集成电路的方法，所述方法包括形成悬置在绝缘体衬底上的第一纳米线，所述第一纳米线附接到绝缘体上的第一绝缘体（SOI）焊盘区域和设置在所述绝缘体衬底上的第二SOI焊盘区域， 布置在绝缘体基板上的第二纳米线，其连接到设置在绝缘体基板上的第三SOI焊盘区域和第四SOI焊盘区域，以及SOI板状区域，其设置在绝缘体基板上，并且形成围绕部分的第一栅极 的第一纳米线，第二纳米线的一部分上的第二栅极和SOI板区域的一部分上的第三栅极。

公开(公告)号：US20130126986A1

公开(公告)日：2013-05-23

申请号：US13300146

申请日：2011-11-18

申请人： MaryJane Brodsky ,  Murshed M. Chowdhury ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Shreesh Narasimha ,  Shahab Siddiqui

发明人： MaryJane Brodsky ,  Murshed M. Chowdhury ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Shreesh Narasimha ,  Shahab Siddiqui

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/518 ,  H01L21/28255 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66575 ,  H01L29/78

摘要： A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

摘要翻译： 一种半导体器件，包括在所述半导体衬底的沟道区上包括栅极结构的含锗衬底。 栅极结构可以包括与含锗衬底的上表面直接接触的氧化硅层，与氧化硅层直接接触的至少一个高k栅介质层和直接与锗氧化物层直接接触的至少一个栅极导体 与高k栅介质层接触。 氧化硅层和含锗衬底的上表面之间的界面基本上不含氧化锗。 源极区域和漏极区域可以存在于沟道区域的相对侧上。

公开(公告)号：US20130087859A1

公开(公告)日：2013-04-11

申请号：US13253268

申请日：2011-10-05

申请人： Yue Liang ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yanfeng Wang

发明人： Yue Liang ,  Dechao Guo ,  William K. Henson ,  Shreesh Narasimha ,  Yanfeng Wang

IPC分类号： H01L21/266 ,  H01L27/092

CPC分类号： H01L27/092 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/517

摘要： A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×1016 atoms/cm3 to 1×1021 atoms/cm3 is present at an interface between the high-k gate dielectric of the gate structure for the n-type semiconductor device and the semiconductor substrate. Methods of forming the aforementioned device are also disclosed.

摘要翻译： 一种在半导体衬底上包括p型半导体器件和n型半导体器件的器件。 n型半导体器件包括具有高k栅极电介质的栅极结构。 在n型半导体器件的栅极结构的高k栅极电介质和半导体衬底之间的界面处存在浓度范围为1×1016原子/ cm3至1×1021原子/ cm3的碳掺杂剂。 还公开了形成上述装置的方法。