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134 条记录 (耗时 0.052 秒)

    Single gate inverter nanowire mesh
    81.
    发明授权
    Single gate inverter nanowire mesh 有权
    单门逆变器纳米线网

    公开(公告)号：US08084308B2

    公开(公告)日：2011-12-27

    申请号：US12470128

    申请日：2009-05-21

    申请人： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

    发明人： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/148 ,  H01L27/105

    CPC分类号： H01L27/1203 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

    摘要： Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

    摘要翻译： 提供基于纳米线的设备。 一方面，提供了场效应晶体管（FET）逆变器。 FET反相器包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个 更多的器件层掺杂有n型掺杂剂，并且器件层中的一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。 还提供了用于制造FET逆变器的技术。

    Nanomesh SRAM Cell
    84.
    发明申请
    Nanomesh SRAM Cell 有权
    Nanomesh SRAM单元

    公开(公告)号：US20110031473A1

    公开(公告)日：2011-02-10

    申请号：US12536741

    申请日：2009-08-06

    申请人： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

    发明人： Josephine Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey Sleight

    IPC分类号： H01L27/11 ,  H01L29/66 ,  H01L21/8239

    CPC分类号： H01L27/1203 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  Y10S977/938

    摘要： Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

    摘要翻译： 提供基于纳米线的设备。 在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。 每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。 每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。

    THIN BODY SILICON-ON-INSULATOR TRANSISTOR WITH BORDERLESS SELF-ALIGNED CONTACTS
    85.
    发明申请
    THIN BODY SILICON-ON-INSULATOR TRANSISTOR WITH BORDERLESS SELF-ALIGNED CONTACTS 审中-公开
    具有无边界自对准接触器的薄体硅绝缘体晶体管

    公开(公告)号：US20100038715A1

    公开(公告)日：2010-02-18

    申请号：US12193392

    申请日：2008-08-18

    申请人： KATHERINA E. BABICH ,  Michael A. Guillorn ,  Isaac Lauer ,  Amlan Majumdar

    发明人： KATHERINA E. BABICH ,  Michael A. Guillorn ,  Isaac Lauer ,  Amlan Majumdar

    IPC分类号： H01L29/72 ,  H01L21/84

    CPC分类号： H01L29/66628 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/78618

    摘要： A method for fabricating a thin-silicon-on-insulator transistor with borderless self-aligned contacts is disclosed. A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack includes a gate oxide layer on the silicon layer and a gate electrode layer on the gate oxide layer. A hard mask on top of the gate stack is formed. An off-set spacer is formed surrounding the gate stack. A raised source/drain region is epitaxially formed adjacent to the off-set spacer. The raised source/drain region is grown slightly about a height of the gate stack including the hard mask. The raised source/drain region forms borderless self-aligned contact.

    摘要翻译： 公开了一种制造具有无边界自对准触点的绝缘体上硅晶体管的方法。 栅极堆叠形成在掩埋氧化物层上方的硅层上。 栅极堆叠包括在硅层上的栅极氧化物层和栅极氧化物层上的栅极电极层。 形成了在栅极堆叠顶部的硬掩模。 在栅堆叠周围形成偏置的间隔物。 凸起的源极/漏极区域与偏置的间隔物相邻地外延形成。 升高的源极/漏极区域围绕包括硬掩模的栅极堆叠的高度略微生长。 升高的源极/漏极区域形成无边界自对准接触。

    MULTI-LAYER MASK METHOD FOR PATTERNED STRUCTURE ETHCING
    86.
    发明申请
    MULTI-LAYER MASK METHOD FOR PATTERNED STRUCTURE ETHCING 审中-公开
    多层结构的多层掩模方法

    公开(公告)号：US20080305437A1

    公开(公告)日：2008-12-11

    申请号：US11760992

    申请日：2007-06-11

    申请人： Nicholas C.M. Fuller ,  Michael A. Guillorn ,  Francois Pagette ,  Balasubramanian Pranatharthiharan ,  Ying Zhang

    发明人： Nicholas C.M. Fuller ,  Michael A. Guillorn ,  Francois Pagette ,  Balasubramanian Pranatharthiharan ,  Ying Zhang

    IPC分类号： G03C5/00

    CPC分类号： H01L21/28123 ,  H01L21/31116 ,  H01L21/32136 ,  H01L29/7833

    摘要： A method for forming a patterned structure within a microelectronic structure uses a non-directly imageable organic material layer located over a substrate and a directly imageable inorganic material layer located upon the non-directly imageable organic material layer. The directly imageable inorganic material layer is directly imaged to form a patterned inorganic material layer. The patterned inorganic material layer is used as a first etch mask within a first etch method that etches the non-directly imageable organic material layer to form a patterned organic material layer. At least the patterned organic material layer is used as a second etch mask within a second etch method that etches the substrate to form a patterned structure within the substrate.

    摘要翻译： 用于在微电子结构内形成图案化结构的方法使用位于基底上的非直接成像的有机材料层和位于不可直接成像的有机材料层上的可直接成像的无机材料层。 可直接成像无机材料层直接成像以形成图案化的无机材料层。 图案化的无机材料层在第一蚀刻方法中用作第一蚀刻掩模，其蚀刻非直接成像的有机材料层以形成图案化的有机材料层。 至少图案化的有机材料层在第二蚀刻方法中用作第二蚀刻掩模，其蚀刻衬底以在衬底内形成图案化结构。

    Method to transfer lithographic patterns into inorganic substrates
    90.
    发明授权
    Method to transfer lithographic patterns into inorganic substrates 有权
    将光刻图案转移到无机基板中的方法

    公开(公告)号：US08658050B2

    公开(公告)日：2014-02-25

    申请号：US13191985

    申请日：2011-07-27

    申请人： Sebastian Ulrich Engelmann ,  Martin Glodde ,  Michael A. Guillorn

    发明人： Sebastian Ulrich Engelmann ,  Martin Glodde ,  Michael A. Guillorn

    IPC分类号： H01L21/302

    CPC分类号： H01L21/0337 ,  G03F7/0043 ,  G03F7/0757 ,  G03F7/094 ,  H01L21/0332

    摘要： Techniques for minimizing or eliminating pattern deformation during lithographic pattern transfer to inorganic substrates are provided. In one aspect, a method for pattern transfer into an inorganic substrate is provided. The method includes the following steps. The inorganic substrate is provided. An organic planarizing layer is spin-coated on the inorganic substrate. The organic planarizing layer is baked. A hardmask is deposited onto the organic planarizing layer. A photoresist layer is spin-coated onto the hardmask. The photoresist layer is patterned. The hardmask is etched through the patterned photoresist layer using reactive ion etching (RIE). The organic planarizing layer is etched through the etched hardmask using RIE. A high-temperature anneal is performed in the absence of oxygen. The inorganic substrate is etched through the etched organic planarizing layer using reactive ion etching.

    摘要翻译： 提供了在将光刻图案转移到无机基底期间最小化或消除图案变形的技术。 一方面，提供了图案转印到无机基板中的方法。 该方法包括以下步骤。 提供无机基材。 将有机平面化层旋涂在无机基材上。 烘烤有机平坦化层。 硬掩模沉积在有机平坦化层上。 将光致抗蚀剂层旋涂在硬掩模上。 对光致抗蚀剂层进行图案化。 使用反应离子蚀刻（RIE），通过图案化的光刻胶层蚀刻硬掩模。 使用RIE蚀刻通过蚀刻的硬掩模的有机平坦化层。 在不存在氧的情况下进行高温退火。 使用反应离子蚀刻通过蚀刻的有机平坦化层蚀刻无机衬底。