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128 条记录 (耗时 0.035 秒)

    Memory cell, pair of memory cells, and memory array
    82.
    发明授权
    Memory cell, pair of memory cells, and memory array 有权
    存储单元，存储单元对和存储器阵列

    公开(公告)号：US08207564B2

    公开(公告)日：2012-06-26

    申请号：US12844045

    申请日：2010-07-27

    申请人： H. Montgomery Manning ,  David H. Wells

    发明人： H. Montgomery Manning ,  David H. Wells

    IPC分类号： H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10885 ,  H01L27/0207 ,  H01L27/10823

    摘要： A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The shared digitline couples with adjacent memory cells, and the plurality of access transistors selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in a substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.

    摘要翻译： 存储器单元，器件和系统包括具有共享数字线的存储单元，存储电容器和被配置为选择性地将存储电容器与共享数字线电耦合的多个存取晶体管。 共享数字线耦合到相邻存储器单元，并且多个存取晶体管选择哪个相邻存储器单元耦合到共享数字线。 形成存储单元的方法包括在衬底中形成掩埋数字线，并且在与衬底数字线相邻的衬底中形成垂直柱。 双栅晶体管形成在垂直柱上，第一端电耦合到掩埋数字线，第二端耦合到形成于其上的存储电容器。

    Integrated Circuitry
    84.
    发明申请
    Integrated Circuitry 有权
    集成电路

    公开(公告)号：US20110210400A1

    公开(公告)日：2011-09-01

    申请号：US13096953

    申请日：2011-04-28

    申请人： David H. Wells ,  Eric R. Blomiley

    发明人： David H. Wells ,  Eric R. Blomiley

    IPC分类号： H01L27/088 ,  H01L27/02

    CPC分类号： H01L29/1083 ,  H01L21/3221 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/11 ,  H01L29/7833 ,  H01L29/7849 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.

    摘要翻译： 一些实施例包括在第一半导体材料中形成至少一个空腔，随后在第一半导体材料上外延生长第二半导体材料并桥接穿过至少一个空腔。 空腔可以保持打开，或者可以在空腔内提供材料。 设置在空腔内的材料可适用于形成例如电磁辐射相互作用部件，晶体管栅极，绝缘结构和冷却剂结构中的一个或多个。 一些实施例包括晶体管器件，电磁辐射相互作用元件，晶体管器件，冷却剂结构，绝缘结构和气体储存器中的一个或多个。

    Electromagnetic radiation conduits
    85.
    发明授权
    Electromagnetic radiation conduits 有权
    电磁辐射导管

    公开(公告)号：US08004055B2

    公开(公告)日：2011-08-23

    申请号：US11724649

    申请日：2007-03-14

    申请人： David H. Wells

    发明人： David H. Wells

    IPC分类号： H01L29/78

    CPC分类号： H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

    摘要： Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

    摘要翻译： 一些实施例包括在半导体结构内形成空隙的方法。 在一些实施例中，空隙可以用作用于分配冷却剂的微结构，用于引导电磁辐射，或用于材料的分离和/或表征。 一些实施例包括其中具有对应于空隙，导管，绝缘结构，半导体结构或导电结构的微结构的结构。

    Integrated circuitry
    86.
    发明授权
    Integrated circuitry 有权
    集成电路

    公开(公告)号：US07956416B2

    公开(公告)日：2011-06-07

    申请号：US12474383

    申请日：2009-05-29

    申请人： David H. Wells ,  Eric R. Blomiley

    发明人： David H. Wells ,  Eric R. Blomiley

    IPC分类号： H01L21/32

    CPC分类号： H01L29/1083 ,  H01L21/3221 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/11 ,  H01L29/7833 ,  H01L29/7849 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.

    摘要翻译： 一些实施例包括在第一半导体材料中形成至少一个空腔，随后在第一半导体材料上外延生长第二半导体材料并桥接穿过至少一个空腔。 空腔可以保持打开，或者可以在空腔内提供材料。 设置在空腔内的材料可适用于形成例如电磁辐射相互作用部件，晶体管栅极，绝缘结构和冷却剂结构中的一个或多个。 一些实施例包括晶体管器件，电磁辐射相互作用元件，晶体管器件，冷却剂结构，绝缘结构和气体储存器中的一个或多个。

    Memory array buried digit line
    89.
    发明授权
    Memory array buried digit line 有权
    存储阵列埋数字线

    公开(公告)号：US07601608B2

    公开(公告)日：2009-10-13

    申请号：US11490619

    申请日：2006-07-21

    申请人： David H. Wells

    发明人： David H. Wells

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10808 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

    摘要： A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.

    摘要翻译： 公开了一种形成掩埋数字线的方法。 牺牲隔离物沿着隔离沟槽的侧壁形成，然后用牺牲材料填充。 一个间隔物被屏蔽，而另一个间隔物被去除，并且在去除的间隔物下方的衬底中的蚀刻步骤形成隔离窗。 然后，绝缘衬垫沿着排空的沟槽的侧壁形成，包括进入隔离窗。 然后在绝缘衬垫之间通过沟槽的底部形成数字线凹槽，这两个绝缘衬垫作为掩模加倍以自对准该蚀刻。 然后，数字线凹槽填充有金属和凹进的后部，并且具有可选的预先绝缘元件，并且沉积在凹部的底部中。

    EPITAXIAL SILICON GROWTH
    90.
    发明申请
    EPITAXIAL SILICON GROWTH 有权
    外延硅增长

    公开(公告)号：US20090095997A1

    公开(公告)日：2009-04-16

    申请号：US12337292

    申请日：2008-12-17

    申请人： David H. Wells ,  Du Li

    发明人： David H. Wells ,  Du Li

    IPC分类号： H01L29/788 ,  H01L29/94

    CPC分类号： H01L29/788 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02639 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7851

    摘要： Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer.

    摘要翻译： 已经描述了包括外延硅生长的方法的包括PSOI，NAND，NOR，FinFET等的存储单元结构和制造方法。 该方法包括在衬底上提供硅层。 在硅层上提供介电层。 在电介质层中形成沟槽以暴露硅层，沟槽具有沿<100>方向的沟槽壁。 该方法包括在形成在电介质层中的沟槽壁之间外延生长硅。