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    Assembly for testing silicon wafers which have a through-via
    82.
    发明授权
    Assembly for testing silicon wafers which have a through-via 失效
    用于测试具有通孔的硅片的组件

    公开(公告)号：US06850084B2

    公开(公告)日：2005-02-01

    申请号：US10253788

    申请日：2002-09-24

    Applicant: David R. Hembree

    Inventor： David R. Hembree

    IPC: H01L21/768 ,  H05K1/03 ,  H05K3/40 ,  G01R31/26

    CPC classification number: H01L21/76898 ,  H05K1/0306 ,  H05K3/4038 ,  Y10T29/49165

    Abstract: A method for filling a via formed through a silicon wafer is disclosed. The method entails mounting the silicon wafer on a mounting substrate and depositing either molten or solid balls of a conductive material into the via. The deposited conductive material may be reflowed to provide electrical contact with other components on the surface of wafer.

    Abstract translation: 公开了一种用于填充通过硅晶片形成的通孔的方法。 该方法需要将硅晶片安装在安装基板上，并将导电材料的熔融或固体球沉积到通孔中。 沉积的导电材料可以回流以提供与晶片表面上的其它部件的电接触。

    Multi-chip module system and method of fabrication
    85.
    发明授权
    Multi-chip module system and method of fabrication 失效
    多芯片模块系统及其制造方法

    公开(公告)号：US06730526B2

    公开(公告)日：2004-05-04

    申请号：US10033234

    申请日：2001-12-28

    Applicant: Salman Akram ,  David R. Hembree ,  James M. Wark

    Inventor： Salman Akram ,  David R. Hembree ,  James M. Wark

    IPC: H01L2100

    CPC classification number: H01L23/5382 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00

    Abstract: Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.

    Abstract translation: 多芯片模块系统及其制造方法，其中将多芯片模块（MCM）的故障芯片的等同物添加到先前用适当的电连接构造的空位中的模块中。 各种不同的骰子可以通过适配器连接到MCM的相同空位，其中每个适配器具有相同的占位面积，但是不同的适配器能够容纳不同数量和类型的骰子。

    Apparatus for forming coaxial silicon interconnects
    86.
    发明授权
    Apparatus for forming coaxial silicon interconnects 失效
    用于形成同轴硅互连的装置

    公开(公告)号：US06646458B2

    公开(公告)日：2003-11-11

    申请号：US10219842

    申请日：2002-08-14

    Applicant: Salman Akram ,  David R. Hembree ,  Alan G. Wood

    Inventor： Salman Akram ,  David R. Hembree ,  Alan G. Wood

    IPC: G01R3102

    CPC classification number: G01R31/2886 ,  G01R1/0408

    Abstract: An interconnect apparatus for testing bare semiconductor dice comprises raised contact members on a semiconductive substrate. The contact members are covered with an insulation layer and a conductive cap connected by a conductive trace to a testing circuit. The trace is covered with coaxial layers of a silicon-containing insulation and a metal for shielding the trace from “crosstalk” and other interference. An apparatus for simultaneous testing of multiple dies on a wafer has thermal expansion characteristics matching those of the semiconductor die or wafer and provides clean signals.

    Abstract translation: 用于测试裸半导体裸片的互连装置包括半导体衬底上的凸起接触构件。 接触构件覆盖有绝缘层和通过导电迹线连接到测试电路的导电盖。 该迹线覆盖有含硅绝缘体和金属的同轴层，用于屏蔽“串扰”和其他干扰的迹线。 用于在晶片上同时测试多个管芯的装置具有与半导体管芯或晶片的热膨胀特性相匹配的热膨胀特性并提供干净的信号。

    Test carrier with molded interconnect for testing semiconductor components
    88.
    发明授权
    Test carrier with molded interconnect for testing semiconductor components 失效
    带有模拟互连的测试载体，用于测试半导体元件

    公开(公告)号：US06544461B1

    公开(公告)日：2003-04-08

    申请号：US09677555

    申请日：2000-10-02

    Applicant: David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

    Inventor： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

    IPC: B29C4502

    CPC classification number: G01R1/0483

    Abstract: A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects. A gasket may be used to protect the interconnect contacts during the molding step.

    Abstract translation: 提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。 载体包括模制塑料基底，引线框架和互连件。 互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。 通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。 替代实施例的载体包括多个互连件模制或层压的板。 另外，夹子构件保持电路板上与组件电连通的组件。 可以在模制步骤期间使用垫圈来保护互连触点。

    Methods of semiconductor processing
    89.
    发明授权
    Methods of semiconductor processing 有权
    半导体加工方法

    公开(公告)号：US06472240B2

    公开(公告)日：2002-10-29

    申请号：US09835052

    申请日：2001-04-13

    Applicant: Salman Akram ,  David R. Hembree

    Inventor： Salman Akram ,  David R. Hembree

    IPC: H01L2166

    CPC classification number: G01K1/026 ,  H01L22/12 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/8592 ,  H01L2924/15156 ,  H01L2924/00014

    Abstract: The present invention includes electronic device workpieces, methods of semiconductor processing and methods of sensing temperature of an electronic device workpiece. In one aspect, the invention provides an electronic device workpiece including: a substrate having a surface; a temperature sensing device borne by the substrate; and an electrical interconnect formed upon the surface of the substrate, the electrical interconnect being electrically coupled with the temperature sensing device. In another aspect, a method of sensing temperature of an electronic device workpiece includes: providing an electronic device workpiece; supporting a temperature sensing device using the electronic device workpiece; providing an electrical interconnect upon a surface of the electronic device workpiece; electrically coupling the electrical interconnect with the temperature sensing device; and sensing temperature of the electronic device workpiece using the temperature sensing device.

    Abstract translation: 本发明包括电子设备工件，半导体处理方法和感测电子设备工件温度的方法。 一方面，本发明提供了一种电子设备工件，包括：具有表面的基板; 由基板承载的温度感测装置; 以及形成在所述基板的表面上的电互连，所述电互连件与所述温度感测装置电耦合。 另一方面，一种感测电子设备工件的温度的方法包括：提供电子设备工件; 支持使用电子设备工件的温度感测装置; 在所述电子设备工件的表面上提供电互连; 将电互连电气耦合到温度感测装置; 以及使用温度感测装置感测电子装置工件的温度。

    Apparatus for forming coaxial silicon interconnects
    90.
    发明授权
    Apparatus for forming coaxial silicon interconnects 失效
    用于形成同轴硅互连的装置

    公开(公告)号：US06469532B2

    公开(公告)日：2002-10-22

    申请号：US10068082

    申请日：2002-02-06

    Applicant: Salman Akram ,  David R. Hembree ,  Alan G. Wood

    Inventor： Salman Akram ,  David R. Hembree ,  Alan G. Wood

    IPC: G01R3102

    CPC classification number: G01R31/2886 ,  G01R1/0408

    Abstract: An interconnect apparatus for testing bare semiconductor dice comprises raised contact members on a semiconductive substrate. The contact members are covered with an insulation layer an a conductive cap connected by a conductive trace to a testing circuit. The trace is covered with coaxial layers of a silicon-containing insulation an a metal for shielding the trace from “crosstalk” and other interference. An apparatus for simultaneous testing of multiple dies on a wafer has thermal expansion characteristic matching those of the semiconductor die or wafer and provides clean signals.

    Abstract translation: 用于测试裸半导体裸片的互连装置包括半导体衬底上的凸起接触构件。 接触构件被绝缘层覆盖，导电盖通过导电迹线连接到测试电路。 迹线覆盖有同轴层的硅含绝缘材料和金属，用于屏蔽“串扰”和其他干扰。 用于在晶片上同时测试多个管芯的装置具有与半导体管芯或晶片匹配的热膨胀特性，并提供干净的信号。

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