公开(公告)号：US09196342B2

公开(公告)日：2015-11-24

申请号：US14676100

申请日：2015-04-01

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1693

Abstract: Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the ends of the selected bit cells are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The ends of the unselected bit cells are held at a precharge voltage while separately timed signals pull up or pull down the ends of the selected bit cells during read and write operations.

Abstract translation: 用于调节施加到自旋转矩磁阻随机存取存储器（ST-MRAM）的磁阻位元的电压的电路和方法降低了字线晶体管的时间依赖介电击穿应力。 在读或写操作期间，根据正在执行的操作（写0，写1和读），仅将所选位单元的端部下拉至低电压和/或上拉至高电压。 未选择的位单元的端部保持在预充电电压，而在读取和写入操作期间单独定时的信号上拉或下拉所选位单元的端部。

公开(公告)号：US09183912B2

公开(公告)日：2015-11-10

申请号：US13892107

申请日：2013-05-10

Applicant: EverSpin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre

IPC: G11C11/16 ,  G11C13/00 ,  G11C5/14

CPC classification number: G11C11/1675 ,  G11C5/147 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697 ,  G11C13/0069 ,  G11C2213/79

Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

Abstract translation: 电池偏置控制电路通过自动调节存储器阵列上的读/写路径的多个控制输入，使存储器单元（磁隧道结器件+晶体管）的读/写路径中的器件的性能最大化，而不会超过泄漏电流或可靠性限制 根据电源电压，温度和过程角变化的预定义配置，通过将任何特定参考参数配置文件应用于存储器阵列。

公开(公告)号：US09183911B2

公开(公告)日：2015-11-10

申请号：US13633479

申请日：2012-10-02

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Chitra Subramanian

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C11/1675 ,  G11C13/004 ,  G11C2013/0057

Abstract: A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation.

Abstract translation: 一种从自旋转矩磁阻存储器阵列中的多个位读取数据的方法包括执行一个或多个参考的比特的读取操作，以及执行自参考的读取操作，例如破坏性的自参考读取操作， 通过引用的读取操作未成功读取的任何位。 引用的读取操作可以在破坏性自引用读取操作的同一时间或之前启动。

公开(公告)号：US20150255137A1

公开(公告)日：2015-09-10

申请号：US14495151

申请日：2014-09-24

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0806 ,  G06F12/0879 ,  G06F2212/62 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/22 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/419 ,  G11C11/5607 ,  Y02D10/13

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.

Abstract translation: 在包括本地源线的自旋扭矩磁随机存取存储器（MRAM）中，字线的自动引导用于通过在写入操作期间重新使用已经存在的驱动多个位线的电荷来节省功耗。 通过首先将字线驱动到第一字线电压来实现自动启动。 经过这样的驾驶，字线隔离。 随后驱动电容耦合到字线的多个位线使得字线电压增加到期望的水平，以允许足够的电流流过选定的存储器单元以将信息写入所选存储单元。 另外的实施例包括使用能够进一步升高或保持隔离字线处于所需电压电平的补充电压提供器。

公开(公告)号：US20150124524A1

公开(公告)日：2015-05-07

申请号：US14595568

申请日：2015-01-13

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Halbert S. Lin

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract translation: 在一些示例中，存储器设备被配置为接收预充电命令和激活命令。 响应于接收到所述预充电命令，响应于接收到所述激活命令，所述存储器装置执行与所述预充电命令相关的第一系列事件和与所述激活命令相关的第二系列事件。 存储器件延迟第二系列事件的开始直到第一系列事件完成。

公开(公告)号：US08976610B2

公开(公告)日：2015-03-10

申请号：US14049844

申请日：2013-10-09

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Halbert S. Lin

IPC: G11C7/00 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract translation: 在一些示例中，存储器设备被配置为接收预充电命令和激活命令。 响应于接收到所述预充电命令，响应于接收到所述激活命令，所述存储器装置执行与所述预充电命令相关的第一系列事件和与所述激活命令相关的第二系列事件。 存储器件延迟第二系列事件的开始直到第一系列事件完成。

公开(公告)号：US20140104963A1

公开(公告)日：2014-04-17

申请号：US14050625

申请日：2013-10-10

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Dietmar Gogl

IPC: G11C7/02 ,  G11C5/14

CPC classification number: G11C7/02 ,  G11C5/14 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C16/12 ,  G11C16/30

Abstract: In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.

Abstract translation: 在一些示例中，存储器件包括配备有隔离开关和专用电源引脚的多个存储体。 每个存储体的隔离开关被配置为将存储体与全局信号隔离。 专用电源引脚被配置为将每个存储器组连接到封装衬底上的专用本地电源焊盘，以向每个存储体提供本地专用电源，并且通过设备上的导体来减少存储体之间的电压传输 ，器件衬底或存储器件的封装衬底。

公开(公告)号：US20140104937A1

公开(公告)日：2014-04-17

申请号：US14049844

申请日：2013-10-09

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Halbert S. Lin

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract translation: 在一些示例中，存储器设备被配置为接收预充电命令和激活命令。 响应于接收到所述预充电命令，响应于接收到所述激活命令，所述存储器装置执行与所述预充电命令相关的第一系列事件和与所述激活命令相关的第二系列事件。 存储器件延迟第二系列事件的开始直到第一系列事件完成。

公开(公告)号：US20130128657A1

公开(公告)日：2013-05-23

申请号：US13633479

申请日：2012-10-02

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Syed M. Alam ,  Thomas Andre ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1675 ,  G11C13/004 ,  G11C2013/0057

Abstract: A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation.

Abstract translation: 一种从自旋转矩磁阻存储器阵列中的多个位读取数据的方法包括执行一个或多个参考的比特的读取操作，以及执行自参考的读取操作，例如破坏性的自参考读取操作， 通过引用的读取操作未成功读取的任何位。 引用的读取操作可以在破坏性自引用读取操作的同一时间或之前启动。

公开(公告)号：US20130128650A1

公开(公告)日：2013-05-23

申请号：US13657002

申请日：2012-10-22

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C11/00

CPC classification number: G11C11/1673 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1084 ,  G11C7/12 ,  G11C11/00 ,  G11C11/02 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1675 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/50008

Abstract: An analog read circuit measures the resistance of each of a plurality of bits in an array of resistive memory elements. Data stored within a latch determines whether to selectively enable the analog read circuit. In an alternate embodiment, a sense amplifier is coupled to the latch and the array, and the data stored in the latch determines whether to selectively enable the sense amplifier.