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    SOI hybrid structure with selective epitaxial growth of silicon
    86.
    发明授权
    SOI hybrid structure with selective epitaxial growth of silicon 有权

    公开(公告)号：US06555891B1

    公开(公告)日：2003-04-29

    申请号：US09690674

    申请日：2000-10-17

    申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

    发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

    IPC分类号： H01L2900

    CPC分类号： H01L27/10894 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1207

    摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

    Method for wrapped-gate MOSFET
    88.
    发明授权
    Method for wrapped-gate MOSFET 失效
    封装栅极MOSFET的方法

    公开(公告)号：US06509611B1

    公开(公告)日：2003-01-21

    申请号：US09961010

    申请日：2001-09-21

    申请人： Byeongju Park ,  Toshiharu Furukawa ,  Jack A. Mandelman

    发明人： Byeongju Park ,  Toshiharu Furukawa ,  Jack A. Mandelman

    IPC分类号： H01L2994

    CPC分类号： H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78618

    摘要： A wrapped-gate transistor includes a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer is formed on the substrate. A gate electrode is formed on the gate dielectric layer to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric therebetween. The substrate is a silicon island formed on an insulation layer of an SOI (silicon-on-insulator) substrate or on a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the “body-to-source” voltage.

    摘要翻译： 包裹栅极晶体管包括具有上表面和彼此相对的第一和第二侧表面的衬底。 源极和漏极区域形成在衬底中，其间具有沟道区域。 沟道区域从衬底的第一侧表面延伸到第二侧表面。 在基板上形成栅介电层。 栅极电极形成在栅极电介质层上，以覆盖来自上表面和第一和第二侧表面的沟道区域，栅电介质在其间。 衬底是形成在SOI（绝缘体上硅）衬底或常规非SOI衬底的绝缘层上的硅岛，并且具有包括第一和第二侧表面的四个侧表面。 源极和漏极区域形成在与第一和第二侧表面垂直的第三和第四侧表面相邻的基板的部分上。 包封门结构在通道区域内提供了更好更快的电位控制，从而产生陡峭的次阈值斜率和对“体对电压”电压的低灵敏度。

    Multi-level dram trench store utilizing two capacitors and two plates
    89.
    发明授权
    Multi-level dram trench store utilizing two capacitors and two plates 失效
    使用两个电容器和两个电路板的多层次的沟渠商店

    公开(公告)号：US06429080B2

    公开(公告)日：2002-08-06

    申请号：US09793517

    申请日：2001-02-27

    申请人： Toshiharu Furukawa ,  David V. Horak ,  Howard L. Kalter

    发明人： Toshiharu Furukawa ,  David V. Horak ,  Howard L. Kalter

    IPC分类号： H01L21336

    CPC分类号： G11C11/565 ,  G11C11/404 ,  H01L27/108 ,  H01L27/10864 ,  H01L27/1087 ,  H01L27/10882

    摘要： A multi-level memory cell capable of storing two or three bits of digital data occupies only four lithographic squares and requires only one or two logic level voltage sources, respectively. High noise immunity derives from integration of the multi-level signal in the memory cell directly from logic level digital signals applied to two capacitors (as well as the bit line for the eight level mode of operation) by using capacitors having different values in order to avoid digital-to-analog conversion during writing. The capacitors can be simultaneously written and read to reduce memory cycle time. Transistor channels and capacitor connections are formed on adjacent semiconductor pillars using plugs of semiconductor material between pillars as common gate structures and connections. Opposite surfaces of the pillars also serve as storage nodes with common capacitor plates formed by conformal deposition between rows of plugs and pillars.

    摘要翻译： 能够存储两位或三位数字数据的多级存储器单元仅占用四个光刻平面，并且仅分别仅需要一个或两个逻辑电平电压源。 通过使用具有不同值的电容器，可以直接从施加到两个电容器的逻辑电平数字信号（以及八电平工作模式的位线）将存储单元中的多电平信号集成到高抗噪声性能 避免在写入过程中进行数模转换。 电容器可以同时写入和读取，以减少存储周期时间。 晶体管通道和电容器连接使用在柱之间的半导体材料的塞子作为公共栅极结构和连接形成在相邻的半导体柱上。 支柱的相对表面还用作具有通过塞子和柱之间的共形沉积形成的公共电容器板的存储节点。