公开(公告)号：US10468525B1

公开(公告)日：2019-11-05

申请号：US15986886

申请日：2018-05-23

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238

摘要： Vertical field effect transistor complementary metal oxide semiconductor (VFET CMOS) structures and methods of fabrication include a single mask level for forming the dual source/drains in both the NFET region and the PFET region. The VFET CMOS structures and methods of fabrication further include equal epi-to-channel distances in both the NFET region and PFET regions.

公开(公告)号：US10367069B2

公开(公告)日：2019-07-30

申请号：US15852956

申请日：2017-12-22

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

摘要： A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.

公开(公告)号：US10361315B1

公开(公告)日：2019-07-23

申请号：US15928325

申请日：2018-03-22

申请人： International Business Machines Corporation

发明人： Chun-Chen Yeh ,  Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita ,  Cheng Chi ,  Chen Zhang

IPC分类号： H01L29/66 ,  H01L29/786 ,  H01L21/8238

摘要： Fabricating a semiconductor device includes receiving a semiconductor structure including a substrate, a fin formed on a portion of the substrate, and a first hard mask disposed on a top surface of the fin. A bottom spacer is formed on the substrate in contact with a bottom portion of the fin. A top spacer is formed in contact with a top portion of the fin. A lateral recess is formed in the substrate under the bottom spacer. A first epitaxy upon the bottom spacer within the lateral recess and a second epitaxy upon the top spacer are simultaneously grown. The first epitaxy forms a bottom source and drain and the second epitaxy forms a top source and drain.

公开(公告)号：US10347719B2

公开(公告)日：2019-07-09

申请号：US16028495

申请日：2018-07-06

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L21/768 ,  H01L29/08 ,  H01L21/306 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8238

摘要： A semiconductor structure. The structure includes first source/drain located in a first source/drain region. The structure includes a second source/drain located in a second source/drain region. The structure includes a plurality of semiconductor nanosheets located between the first source/drain and the second source/drain in a gate region. The structure includes an insulating layer separating the first source drain from a bulk substrate. The bulk substrate may have a first horizontal surface in the gate region, a second horizontal surface in the first source/drain region, and a connecting surface forming an at least partially vertical connection between the first horizontal surface and the second horizontal surface. The insulating layer may be directly on the second horizontal surface and the connecting surface.

公开(公告)号：US20190140052A1

公开(公告)日：2019-05-09

申请号：US16233825

申请日：2018-12-27

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Cheng Chi ,  Chi-Chun Liu ,  Ruilong Xie ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827

摘要： Techniques for VFET top source and drain epitaxy are provided. In one aspect, a method of forming a VFET includes: patterning a fin to form a bottom source/drain region and a fin channel of the VFET; forming bottom spacers on the bottom source/drain region; depositing a high-κ gate dielectric onto the bottom spacers and along sidewalls of the fin channel; forming gates over the bottom spacers; forming top spacers on the gates; partially recessing the fin channel to create a trench between the top spacers; forming a nitride liner along sidewalls of the trench; fully recessing the fin channel through the trench such that side portions of the fin channel remain intact; and forming a doped epitaxial top source and drain region over the fin channel. Methods not requiring a nitride liner and VFET formed using the present techniques are also provided.

公开(公告)号：US10249714B2

公开(公告)日：2019-04-02

申请号：US15634411

申请日：2017-06-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  RENESAS ELECTRONICS CORPORATION

发明人： Dechao Guo ,  Shogo Mochizuki ,  Andreas Scholze ,  Chun-Chen Yeh

IPC分类号： H01L29/08 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/225 ,  H01L21/324 ,  H01L27/088 ,  H01L29/267

摘要： A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

公开(公告)号：US20190005382A1

公开(公告)日：2019-01-03

申请号：US15820114

申请日：2017-11-21

申请人： International Business Machines Corporation

发明人： Yulong Li ,  Paul Solomon ,  Effendi Leobandung ,  Chun-Chen Yeh ,  Seyoung Kim

IPC分类号： G06N3/063 ,  G06F17/16 ,  G06N3/08

摘要： A CMOS-based resistive processing unit (RPU) and method for a neural network. The RPU includes a capacitor device configured to store a charge representing a weight value associated with a neural network circuit operation. A current source Field Effect Transistor (FET) device is operatively connected to the capacitor device for increasing a charge on the capacitor. A current sink FET device operatively connected to the capacitor device is configured for decreasing the stored capacitor charge. An analog weight update circuit receives one or more update signals generated in conjunction with the neural network circuit operation, the analog weight update circuit controlling the current source FET device and the current sink FET device to provide either a determined amount of current to increase the stored charge on the capacitor device, or sink a determined amount of current to decrease the stored charge on the capacitor device.

公开(公告)号：US10170364B2

公开(公告)日：2019-01-01

申请号：US15840344

申请日：2017-12-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Juntao Li ,  Chun-Chen Yeh

IPC分类号： H01L21/338 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06 ,  H01L29/08 ,  H01L21/306 ,  H01L21/308 ,  H01L27/088 ,  H01L27/092 ,  H01L21/84

摘要： A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

公开(公告)号：US10128335B2

公开(公告)日：2018-11-13

申请号：US15229593

申请日：2016-08-05

申请人： International Business Machines Corporation

发明人： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L21/84 ,  H01L21/3115 ,  H01L29/66 ,  H01L29/417 ,  H01L21/311 ,  H01L29/786 ,  H01L21/02 ,  H01L29/78 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/3105 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167

摘要： A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried oxide layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.

公开(公告)号：US09991255B2

公开(公告)日：2018-06-05

申请号：US14661590

申请日：2015-03-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

发明人： Hong He ,  Shogo Mochizuki ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC分类号： H01L27/088 ,  H01L29/04 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/08

CPC分类号： H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

摘要： Semiconductor devices having non-merged fin extensions. A semiconductor device includes fins formed in trenches in an insulator layer, each of the fins having a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another.