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    Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
    82.
    发明授权
    Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein 有权
    在层的上表面和驻留在其中的导电结构之间实现更大的平坦度

    公开(公告)号：US08883020B2

    公开(公告)日：2014-11-11

    申请号：US13754170

    申请日：2013-01-30

    Applicant: Globalfoundries, Inc.

    Inventor： Xunyuan Zhang ,  Xiuyu Cai

    IPC: B44C1/22 ,  H05K3/00

    CPC classification number: H01L21/3212 ,  C09G1/02 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76888 ,  H01L23/53228 ,  H01L45/1633 ,  H01L2924/0002 ,  H05K3/00 ,  H05K3/26 ,  H05K2201/0376 ,  H05K2203/0346 ,  H01L2924/00

    Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

    Abstract translation: 在导电结构的表面和导电结构所在的层之间实现更大的平坦度。 突出在层表面之上的导电结构的一部分被至少部分地选择性地氧化以形成氧化部分。 至少部分地去除氧化部分，以便于实现更大的平坦度。 当导电结构最初凹陷在层的表面下方时，可以可选地通过在导电结构上方选择性地设置导电材料来形成突出部分。 另一个实施例包括选择性地将导电结构的一部分氧化在该层的表面之下，去除至少一些氧化部分，使得导电结构的上表面在该层的上表面之下，并平坦化上表面 的层到导电结构的上表面。

    Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting device
    84.
    发明授权
    Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting device 有权
    使用没有阻挡层的铜基氮化物种子层形成导电铜基结构的方法和所得到的器件

    公开(公告)号：US08753975B1

    公开(公告)日：2014-06-17

    申请号：US13757288

    申请日：2013-02-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

    IPC: H01L21/4763

    CPC classification number: H01L21/76873 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method includes forming a trench/via in a layer of insulating material, forming a first layer comprised of silicon or germanium on the insulating material in the trench/via, forming a copper-based seed layer on the first layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based nitride layer positioned between the copper-based conductive structure and the layer of insulating material, wherein the copper-based nitride layer contacts both of the copper-based conductive structure and the layer of insulating material.

    Abstract translation: 一种方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中的绝缘材料上形成由硅或锗构成的第一层，在第一层上形成铜基种子层，至少转化为 铜基种子层的一部分成为铜基氮化物层，在铜基氮化物层上沉积大量铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺以除去过量的 位于沟槽/通孔外部的材料，从而限定铜基导电结构。 一种器件包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和绝缘材料层之间的铜基氮化物层，其中 铜基氮化物层接触铜基导电结构和绝缘材料层。

    INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE
    85.
    发明申请
    INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE 有权
    集成电路和方法制造集成电路，降低PARASIIC电容

    公开(公告)号：US20140138779A1

    公开(公告)日：2014-05-22

    申请号：US13682331

    申请日：2012-11-20

    Applicant: GLOBALFOUNDRIES, INC.

    Inventor： Ruilong Xie ,  Xiuyu Cai ,  Xunyuan Zhang

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40

    CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/4991 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/78

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

    Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成牺牲栅极结构。 在牺牲栅极结构周围形成间隔物，并且在间隔物和半导体衬底上沉积电介质材料。 该方法包括选择性地蚀刻间隔物以在牺牲栅极结构和电介质材料之间形成沟槽。 沟槽由沟槽表面限定，在该沟槽表面上沉积替代间隔物材料。 该方法合并替换间隔物材料的上部区域以在替换间隔物材料内包围空隙。

    Devices and methods of forming low resistivity noble metal interconnect
    86.
    发明授权
    Devices and methods of forming low resistivity noble metal interconnect 有权

    公开(公告)号：US10679937B2

    公开(公告)日：2020-06-09

    申请号：US15785665

    申请日：2017-10-17

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528

    Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

    Via and skip via structures
    87.
    发明授权
    Via and skip via structures 有权

    公开(公告)号：US10485111B2

    公开(公告)日：2019-11-19

    申请号：US15647400

    申请日：2017-07-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Shao Beng Law ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  James McMahon ,  Ryan S. Smith ,  Xunyuan Zhang

    IPC: H05K3/46 ,  H05K3/40 ,  H05K1/11 ,  H01L21/768

    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

    METHODS OF PROTECTING STRUCTURE OF INTEGRATED CIRCUIT FROM REWORK
    88.
    发明申请
    METHODS OF PROTECTING STRUCTURE OF INTEGRATED CIRCUIT FROM REWORK 审中-公开

    公开(公告)号：US20190318927A1

    公开(公告)日：2019-10-17

    申请号：US15954066

    申请日：2018-04-16

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Lei Sun ,  Xunyuan Zhang ,  Frank W. Mont ,  Shao Beng Law

    IPC: H01L21/033 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02

    Abstract: The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.

    Method of forming a vertical field effect transistor (VFET) and a VFET structure
    89.
    发明授权
    Method of forming a vertical field effect transistor (VFET) and a VFET structure 有权

    公开(公告)号：US10276689B2

    公开(公告)日：2019-04-30

    申请号：US15615925

    申请日：2017-06-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Ruilong Xie ,  Xunyuan Zhang ,  Hui Zang

    IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

    Abstract: Disclosed are embodiments of an improved method for forming a vertical field effect transistor (VFET). In each of the embodiments of the method, a semiconductor fin is formed sufficiently thick (i.e., wide) so that the surface area of the top of the semiconductor fin is sufficiently large to facilitate epitaxial growth thereon of a semiconductor material for a second source/drain region. As a result, the second source/drain region will be sufficiently large to avoid potential contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.). Additionally, either before or after this second source/drain region is formed, at least the center portion of the semiconductor fin, which will include the channel region of the VFET, is thinned down to a desired critical dimension for optimal VFET performance. Also disclosed are VFET structure embodiments resulting from this method.

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