公开(公告)号：US20160204261A1

公开(公告)日：2016-07-14

申请号：US15073936

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Witold P. Maszara ,  Jody A. Fronheiser

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/30604 ,  H01L21/32133 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/51 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract translation: 公开了在半导体器件的沟道区域中形成外延半导体包层材料的一种方法，其包括围绕初始鳍片的一部分形成牺牲栅极结构，在牺牲栅极结构的相对侧上形成侧壁间隔物，并去除牺牲栅极 结构，从而限定替换栅极腔，通过替代栅极腔执行蚀刻工艺以去除初始翅片的部分，从而限定在侧壁间隔物下方的减小尺寸的翅片和凹陷，形成至少一个替代外延半导体 在更换的浇口腔体和侧壁间隙的凹槽内围绕减小尺寸的翅片的覆层材料，以及在至少一个替代的外延半导体包层材料周围的置换栅极腔内形成替换栅极结构。

公开(公告)号：US09343300B1

公开(公告)日：2016-05-17

申请号：US14686857

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Michael Hargrove ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/66 ,  H01L21/324 ,  H01L29/167 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/225

CPC classification number: H01L29/66636 ,  H01L21/02579 ,  H01L21/02694 ,  H01L21/2251 ,  H01L21/2257 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: The present disclosure is directed to forming relatively abrupt junctions between the channel region and source/drain regions of a PMOS transistor device with a germanium-containing channel region. A liner layer is formed in previously formed source/drain cavities prior to the formation of epi semiconductor material in the source/drain cavities above the liner layer. The materials for the liner layer and, particularly, the concentration of germanium (if any is present) are adjusted relative to the germanium concentration in the channel region and the epi source/drain material such that, during an anneal process, dopant materials (e.g., boron) that diffuse from the source/drain region during the anneal process tend to accumulate in or near the liner layer.

Abstract translation: 本公开涉及在具有含锗沟道区的PMOS晶体管器件的沟道区域和源极/漏极区域之间形成相对突然的结。 在预先形成的源/漏腔之前，在衬层之上的源极/漏极腔中形成外延半导体材料之前形成衬层。 用于衬里层的材料，特别是锗的浓度（如果有的话）相对于沟道区域和外延源/漏极材料中的锗浓度进行调节，使得在退火过程期间，掺杂剂材料（例如 ，硼）在退火工艺期间从源极/漏极区扩散倾向于积聚在衬里层中或其附近。

公开(公告)号：US20160118251A1

公开(公告)日：2016-04-28

申请号：US14525351

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.

Abstract translation: 本文中公开的一种说明性方法包括进行第一和第二原位掺杂，外延沉积工艺以分别在半导体衬底之上形成第一和第二层原位掺杂的外延半导体材料，其中第一和第二 层具有高水平的锗和低水平的P型掺杂剂材料，并且第一和第二层中的另一层具有低水平的锗和高水平的P型掺杂剂材料，并且进行混合热退火工艺 在第一和第二层上形成具有高水平的锗和高水平的P型掺杂剂材料的最终硅锗材料。

公开(公告)号：US09324790B2

公开(公告)日：2016-04-26

申请号：US14083571

申请日：2013-11-19

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  Renesas Electronics Corporation

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract translation: 形成半导体结构的方法包括在第一组鳍片的翅片之间以及在第二组鳍片的翅片之间形成第一隔离区域。 第一组翅片形成在体半导体衬底中。 第二隔离区域形成在第一散热片组和第二散热片组之间，第二隔离区域延伸穿过第一隔离区域的一部分，使得第一隔离区域和第二隔离区域直接接触并且高于主体 第二隔离区域的半导体衬底大于第一隔离区域的体半导体衬底上方的高度。

公开(公告)号：US09318552B2

公开(公告)日：2016-04-19

申请号：US14283404

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor, Jr. ,  Ajey Poovannummoottil Jacob

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L29/78618 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: One illustrative method disclosed herein includes, among other things, forming a first epi semiconductor material in a source/drain region of a transistor device, the first epi semiconductor material having a first lateral width at an upper surface thereof, forming a second epi semiconductor material on the first epi semiconductor material and above at least a portion of one of a gate cap layer or one of the sidewall spacers of the device, wherein the second epi semiconductor material has a second lateral width at an upper surface thereof that is greater than the first lateral width, and forming a metal silicide region on the upper surface of the second epi semiconductor material.

Abstract translation: 本文公开的一种说明性方法包括在晶体管器件的源极/漏极区域中形成第一外延半导体材料，第一外延半导体材料在其上表面具有第一横向宽度，形成第二外延半导体材料 在所述第一外延半导体材料上以及所述器件的所述侧壁间隔物中的至少一部分栅极帽层或所述侧壁间隔物中的至少一部分，其中所述第二外延半导体材料在其上表面处具有大于 第一横向宽度，并且在第二外延半导体材料的上表面上形成金属硅化物区域。

公开(公告)号：US09312387B2

公开(公告)日：2016-04-12

申请号：US14069955

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Michael Hargrove ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.

Abstract translation: 公开了涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 本文公开的方法和装置包括形成掺杂的硅衬底鳍片，然后在衬底鳍片周围形成硅/锗层。 所述方法和装置还包括使用栅极第一或栅极末端技术在硅/锗层周围形成栅极结构。

公开(公告)号：US09305846B2

公开(公告)日：2016-04-05

申请号：US14599873

申请日：2015-01-19

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/02 ,  H01L21/266 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

公开(公告)号：US20160071930A1

公开(公告)日：2016-03-10

申请号：US14477096

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material.

Abstract translation: 一种方法包括在基底上形成第一定向自组装材料。 使用第一定向自组装材料对衬底进行构图，以限定半导体衬底中的至少一个鳍。 第二定向自组装材料形成在至少一个翅片上方以暴露至少一个翅片的顶表面。 在至少一个翅片的顶表面上形成基本垂直的纳米线。 垂直纳米线的至少第一尺寸由第一定向自组装材料的固有间距限定，并且垂直纳米线的第二尺寸由第二定向自组装材料的固有间距限定。

公开(公告)号：US20160071845A1

公开(公告)日：2016-03-10

申请号：US14476879

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/306 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/823487 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在翅片上形成硬掩模层。 第一定向自组装材料形成在硬掩模层之上。 使用第一定向自组装材料的一部分作为蚀刻掩模对硬掩模层进行图案化，以暴露鳍的顶表面的一部分。 在暴露的顶表面上形成基本垂直的纳米线。 基本垂直的纳米线的至少一个维度由第一定向自组装材料的固有间距限定。

公开(公告)号：US09252208B1

公开(公告)日：2016-02-02

申请号：US14447678

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  GLOBALFOUNDRIES Inc.

Inventor： Pierre Morin ,  Maud Vinet ,  Laurent Grenouillet ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/1066 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.