利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

135 条记录 (耗时 0.023 秒)

    FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION
    81.
    发明申请
    FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION 有权
    场效应晶体管和制造方法

    公开(公告)号：US20150001642A1

    公开(公告)日：2015-01-01

    申请号：US14476073

    申请日：2014-09-03

    申请人： GLOBALFOUNDRIES INC.

    发明人： Hoon Kim ,  Kisik Choi ,  Chanro Park

    IPC分类号： H01L29/49 ,  H01L29/423

    CPC分类号： H01L29/4966 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

    摘要： An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.

    摘要翻译： 公开了一种改进的场效应晶体管及其制造方法。 在栅腔的基底和侧壁中形成阻挡层堆叠。 阻挡层堆叠具有第一金属层和第二金属层。 栅极电极金属沉积在空腔中。 阻挡层堆叠在栅极腔的侧壁上变薄或去除，以更精确地控制场效应晶体管的电压阈值。

    Hard mask layer to reduce loss of isolation material during dummy gate removal
    83.
    发明授权
    Hard mask layer to reduce loss of isolation material during dummy gate removal 有权

    公开(公告)号：US10446399B2

    公开(公告)日：2019-10-15

    申请号：US15339497

    申请日：2016-10-31

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

    IPC分类号： H01L21/28 ,  H01L29/66 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/311

    摘要： A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes. A resulting semiconductor structure formed by the method is also provided.

    Methods of forming a gate contact for a transistor above the active region and an air gap adjacent the gate of the transistor
    84.
    发明授权
    Methods of forming a gate contact for a transistor above the active region and an air gap adjacent the gate of the transistor 有权

    公开(公告)号：US10177241B2

    公开(公告)日：2019-01-08

    申请号：US15337254

    申请日：2016-10-28

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

    IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L21/28 ,  H01L21/3213

    摘要： One illustrative method disclosed includes, among other things, removing a portion of an initial gate cap layer and a portion of an initial sidewall spacer so as to thereby define a gate contact cavity that exposes a portion of a gate structure, completely forming a conductive gate contact structure (CB) in a gate contact cavity, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region. The method also comprises removing the remaining portion of the initial gate cap layer and to recess a vertical height of exposed portions of the initial sidewall spacer to thereby define a recessed sidewall spacer and a gate cap cavity and forming a replacement gate cap layer in the gate cap cavity so as to define an air space between an upper surface of the recessed sidewall spacer and a lower surface of the replacement gate cap layer.

    METHOD TO TUNE CONTACT CD AND REDUCE MASK COUNT BY TILTED ION BEAM
    90.
    发明申请
    METHOD TO TUNE CONTACT CD AND REDUCE MASK COUNT BY TILTED ION BEAM 审中-公开

    公开(公告)号：US20180047564A1

    公开(公告)日：2018-02-15

    申请号：US15233445

    申请日：2016-08-10

    申请人： GLOBALFOUNDRIES, Inc.

    发明人： Chanro Park ,  Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie

    IPC分类号： H01L21/027 ,  H01L21/306 ,  H01L21/263

    CPC分类号： H01L21/263 ,  H01L21/0338 ,  H01L21/31122 ,  H01L21/31144

    摘要： A novel method of processing and fabricating semiconductor devices is provided to reduce critical dimensions inherent in a given photolithography process. A patterned mask layer generated via transfer of the pattern to the masking layer (e.g., printing) has a given set of dimensions. The method or process forms multiple layers beneath a masking layer. The multiple layers are etched to form openings therein according to the original mask pattern. Thereafter, one of the multiple layers is etched along its sidewalls to increase the opening therethrough, and this layer is utilized as the mask layer for the underlying semiconductor substrate. This enables a reduction in the critical dimensions, at least a critical dimension related to spacing between two features.