公开(公告)号：US20090251988A1

公开(公告)日：2009-10-08

申请号：US12061045

申请日：2008-04-02

申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Warren E. Maule ,  Kenneth L. Wright

发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Warren E. Maule ,  Kenneth L. Wright

IPC分类号： G11C8/00

CPC分类号： G11C5/00 ,  G11C7/1018

摘要： A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.

摘要翻译： 提供了一种用于非二次突发长度的存储器系统，存储器接口装置和方法。 存储器系统包括具有非二次突发长度逻辑的多个存储器件和包括非二次突发长度生成逻辑的存储器接口器件。 非功率二突发长度生成逻辑从两个功率值扩展突发长度，以将错误检测码插入到存储器接口设备和多个存储器件之间的数据线上的突发中。

公开(公告)号：US07593288B2

公开(公告)日：2009-09-22

申请号：US11959711

申请日：2007-12-19

申请人： Kyu-hyoun Kim ,  Paul W. Coteus

发明人： Kyu-hyoun Kim ,  Paul W. Coteus

IPC分类号： G11C7/00

CPC分类号： G11C5/04 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03L7/07 ,  H03L7/0812

摘要： A system for providing read clock sharing between memory devices. The system includes a memory device having an external clock receiver, a read clock receiver, and a phase comparator. The phase comparator synchronizes an internal read clock generated at the memory device. The phase comparator additionally synchronizes one of an external clock received by the external clock receiver and an external read clock received by the read clock receiver. The results of the synchronizing are utilized to refresh the internal read clock. The memory device also includes a mechanism, a read clock driver and a mode register fit. The mechanism is utilized to select between the external clock and the external read clock as input to the phase comparator. The read clock driver outputs the internal read clock generated at the memory device to a read clock output pin. The mode register bit controls the selection of the mechanism, the enabling and disabling of the read clock receiver and the enabling and disabling of the read clock driver.

摘要翻译： 一种用于在存储器件之间提供读时钟共享的系统。 该系统包括具有外部时钟接收器，读取时钟接收器和相位比较器的存储器件。 相位比较器同步存储器件产生的内部读时钟。 相位比较器还将由外部时钟接收器接收到的外部时钟和由读取时钟接收器接收到的外部读取时钟之一进行同步。 利用同步的结果刷新内部读时钟。 存储器件还包括机构，读时钟驱动器和模式寄存器配合。 该机制用于在外部时钟和外部读取时钟之间选择作为相位比较器的输入。 读时钟驱动器将存储器件产生的内部读时钟输出到读时钟输出引脚。 模式寄存器位控制机制的选择，读时钟接收器的使能和禁止以及读时钟驱动器的使能和禁止。

公开(公告)号：US20080285697A1

公开(公告)日：2008-11-20

申请号：US11749409

申请日：2007-05-16

申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Daniel M. Dreps

发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Daniel M. Dreps

IPC分类号： H03D3/24

CPC分类号： H03K5/151 ,  H03K5/13 ,  H03K2005/00052 ,  H03K2005/00234

摘要： A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.

摘要翻译： 一种用于提供开环正交时钟生成的系统。 该系统由环形振荡器结构实现，该环形振荡器结构包括用于接收输入时钟的输入反相器，正向环路逆变器，反向环路逆变器，一个或多个输出以及连接在任何两个相对节点之间的交叉耦合的锁存器。

公开(公告)号：US20070146043A1

公开(公告)日：2007-06-28

申请号：US11679375

申请日：2007-02-27

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03L5/00

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

摘要翻译： 提供了使用电平降低移位器的接口电路和信号钳位电路。 接口电路包括由第一电源驱动的第一电源电路和由第二电源驱动的第二电源电路之间的电平降低移位器。 电平降低移位器将具有第一功率的电压电平的第一电源电路的输出转换为第二功率的电压电平的输出。 电平降低移位器包括第一电路单元，第二电路单元，第三电路单元和第四电路单元。 第一电路单元由第一电源驱动并接收第一电源电路的输出。 第二电路单元由第二电源驱动并接收第一电源电路的输出。 第三电路单元由第二电源驱动并接收第一电源电路的输出。 第四电路单元由第二电源驱动，接收第三电路单元的输出，并连接到第二电路单元的输出端。

公开(公告)号：US20070139093A1

公开(公告)日：2007-06-21

申请号：US11679519

申请日：2007-02-27

申请人： Jae-hyung Lee ,  Kyu-hyoun Kim

发明人： Jae-hyung Lee ,  Kyu-hyoun Kim

IPC分类号： H03L5/00

CPC分类号： H04L25/45 ,  H03K3/356104 ,  H03K3/356113 ,  H03K19/00323 ,  H03K19/018521

摘要： Provided are an interface circuit and a signal clamping circuit using a level-down shifter. The interface circuit includes the level-down shifter between a first power circuit driven by a first power and a second power circuit driven by a second power. The level-down shifter converts an output of the first power circuit that has a voltage level of the first power into an output of a voltage level of the second power. The level-down shifter includes a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit. The first circuit unit is driven by the first power and receives the output of the first power circuit. The second circuit unit is driven by the second power and receives the output of the first power circuit. The third circuit unit is driven by the second power and receives the output of the first power circuit. The fourth circuit unit is driven by the second power, receives an output of the third circuit unit, and is connected to an output of the second circuit unit.

公开(公告)号：US07199630B2

公开(公告)日：2007-04-03

申请号：US11158013

申请日：2005-06-21

申请人： Kyu-hyoun Kim

发明人： Kyu-hyoun Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/081 ,  H03L7/0995

摘要： Delay locked loops include a ring oscillator having serially connected inverters and a feedback path around the serially connected converters. The ring oscillator is configured to generate an output clock signal that is a delayed version of an input clock signal, in response to the input clock signal and to a control signal that is applied to the ring oscillator. A phase responsive circuit is configured to generate the control signal in response to a phase difference between the input clock signal and the output clock signal. Analogous methods of delaying a clock signal also are described.

摘要翻译： 延迟锁定环路包括具有串联连接的反相器的环形振荡器和串联连接的转换器周围的反馈路径。 环形振荡器被配置为响应于输入时钟信号和施加到环形振荡器的控制信号而产生作为输入时钟信号的延迟版本的输出时钟信号。 相位响应电路被配置为响应于输入时钟信号和输出时钟信号之间的相位差而产生控制信号。 还描述了延迟时钟信号的类似方法。

公开(公告)号：US20060076992A1

公开(公告)日：2006-04-13

申请号：US11158013

申请日：2005-06-21

申请人： Kyu-hyoun Kim

发明人： Kyu-hyoun Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/081 ,  H03L7/0995

摘要： Delay locked loops include a ring oscillator having serially connected inverters and a feedback path around the serially connected converters. The ring oscillator is configured to generate an output clock signal that is a delayed version of an input clock signal, in response to the input clock signal and to a control signal that is applied to the ring oscillator. A phase responsive circuit is configured to generate the control signal in response to a phase difference between the input clock signal and the output clock signal. Analogous methods of delaying a clock signal also are described.

摘要翻译： 延迟锁定环路包括具有串联连接的反相器的环形振荡器和串联连接的转换器周围的反馈路径。 环形振荡器被配置为响应于输入时钟信号和施加到环形振荡器的控制信号而产生作为输入时钟信号的延迟版本的输出时钟信号。 相位响应电路被配置为响应于输入时钟信号和输出时钟信号之间的相位差而产生控制信号。 还描述了延迟时钟信号的类似方法。

公开(公告)号：US06980036B2

公开(公告)日：2005-12-27

申请号：US10671105

申请日：2003-09-25

申请人： Kyoung-hwan Kwon ,  Hyun-soon Jang ,  Kyu-hyoun Kim

发明人： Kyoung-hwan Kwon ,  Hyun-soon Jang ,  Kyu-hyoun Kim

IPC分类号： G06F1/04 ,  G11C11/40 ,  G11C29/00 ,  G11C29/12 ,  H03B1/00 ,  H03B19/00 ,  H03B19/10 ,  H03K5/00 ,  H03K5/1534 ,  H03K21/10

CPC分类号： H03K5/1534 ,  H03K5/00006

摘要： In a frequency multiplier and a method of multiplying a frequency of an external clock signal, a data output buffer, and a semiconductor device including the frequency multiplier and the data output buffer, the frequency multiplier receives an external clock signal having a predetermined frequency and outputs an internal clock signal having greater frequency than the predetermined frequency. In the semiconductor device, the data output buffer outputs data tested in response to test data. Therefore, it is possible to test a plurality of memory cells at a time by using a clock signal having a low frequency. In addition, the time and cost required for the test can be greatly reduced, and conventional testing equipment that operates at a relatively low frequency can be effectively used.

摘要翻译： 在频率倍增器和将外部时钟信号的频率，数据输出缓冲器和包括倍频器和数据输出缓冲器的半导体器件相乘的方法中，倍频器接收具有预定频率的外部时钟信号并输出 具有比预定频率更大的频率的内部时钟信号。 在半导体器件中，数据输出缓冲器输出根据测试数据测试的数据。 因此，可以通过使用具有低频率的时钟信号来一次测试多个存储单元。 此外，可以大大降低测试所需的时间和成本，并且可以有效地使用在较低频率下工作的常规测试设备。

公开(公告)号：US20050116746A1

公开(公告)日：2005-06-02

申请号：US10990412

申请日：2004-11-18

申请人： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

发明人： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

IPC分类号： H03K19/0175 ,  H03K19/003 ,  H03B1/00

CPC分类号： H03K19/003

摘要： An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level. The level control section may generate a control signal which maintains the output node at the first level, in response to the level output signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level of the first voltage and may intercept the control signal when the voltage level of the reference voltage signal is equal to the predetermined voltage level.

摘要翻译： 输入缓冲器，用于检测输入信号。 输入缓冲器包括输出节点，第一缓冲器和第二缓冲器。 当参考电压信号的电压电平等于预定电压电平时，第一缓冲器可以控制输出节点的电压电平。 当参考电压信号的电压电平低于预定电压电平时，第二缓冲器可以响应于输入信号来控制输出节点的电压电平。 第二缓冲器可以将输出节点维持在第一级。 第二缓冲器可以包括输出控制部分和电平控制单元。 输出控制部分可以接收输入信号并产生第二电平的电平输出信号。 当参考电压信号的电压电平低于第一电压的预定电压电平时，电平控制部分可以响应于电平输出信号而产生将输出节点维持在第一电平的控制信号，并且可以拦截 当参考电压信号的电压电平等于预定电压电平时，控制信号。

公开(公告)号：US06466071B2

公开(公告)日：2002-10-15

申请号：US09826566

申请日：2001-04-05

申请人： Kyu-hyoun Kim ,  Jung-bae Lee

发明人： Kyu-hyoun Kim ,  Jung-bae Lee

IPC分类号： H03K3017

CPC分类号： H03K5/1565 ,  H03K5/133 ,  H03L7/0812 ,  H03L2207/12 ,  Y10S331/02

摘要： A signal is duty-cycle corrected by delaying the signal to generate a delayed version of the signal and generating an output signal that transitions from a first state to a second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state. The output signal transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.

摘要翻译： 通过延迟信号以产生信号的延迟版本并产生响应于信号从第一状态到第二状态的转变而从第一状态转变到第二状态的输出信号来对信号进行占空比校正， 将信号的延迟版本从第二状态转换到第一状态。 响应于信号从第二状态到第一状态的转变以及信号从第一状态到第二状态的延迟版本的转变，输出信号从第二状态转变到第一状态。