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    Hybrid CMOS nanowire mesh device and FINFET device
    81.
    发明授权
    Hybrid CMOS nanowire mesh device and FINFET device 有权
    混合CMOS纳米线网格器件和FINFET器件

    公开(公告)号：US09230989B2

    公开(公告)日：2016-01-05

    申请号：US14194762

    申请日：2014-03-02

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Leland Chang ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    IPC: H01L29/66 ,  H01L27/12 ,  H01L21/28 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L27/1203 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/28 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

    Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins.

    Abstract translation: SOI衬底上的半导体混合结构。 包含纳米线网状器件的SOI衬底的第一部分和包含FINFET器件的SOI衬底的第二部分。 纳米线网状器件包括位于衬底上的层叠和间隔开的半导体纳米线，每个半导体纳米线具有两个端部段，其中一个端部段连接到源极区域，另一个端部段连接到漏极区域; 以及在所述堆叠并间隔开的半导体纳米线的至少一部分上的栅极区域，其中每个源极区域和每个漏极区域与栅极区域自对准。 FINFET器件包括在衬底的第二部分上的顶部半导体层上的间隔开的翅片; 以及在所述鳍片的至少一部分上方的栅极区域。

    STRAINED SEMICONDUCTOR NANOWIRE
    84.
    发明申请
    STRAINED SEMICONDUCTOR NANOWIRE 有权
    应变半导体纳米级

    公开(公告)号：US20150179781A1

    公开(公告)日：2015-06-25

    申请号：US14135668

    申请日：2013-12-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    IPC: H01L29/775 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

    CPC classification number: H01L29/7848 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

    Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.

    Abstract translation: 在绝缘体层上形成由一对半导体焊盘部分横向邻接的至少一个半导体纳米线。 从至少一个半导体纳米线下方蚀刻绝缘体层的一部分，使得至少一个半导体纳米线被悬浮。 临时填充材料沉积在至少一个半导体纳米线上，并且被平坦化以物理地暴露该对半导体焊盘部分的顶表面。 沟槽形成在该对半导体焊盘部分内，并且填充有应力产生材料。 随后取出临时填充材料。 所述至少一个半导体纳米线在拉伸应变或压缩应变下沿长度方向应变。

    GRAPHENE SENSOR
    86.
    发明申请
    GRAPHENE SENSOR 有权
    石墨传感器

    公开(公告)号：US20150137078A1

    公开(公告)日：2015-05-21

    申请号：US14604959

    申请日：2015-01-26

    Applicant: International Business Machines Corporation

    Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

    IPC: G01N27/414 ,  H01L51/00 ,  H01L29/16

    CPC classification number: G01N27/4145 ,  G01N27/4146 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0048

    Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

    Abstract translation: 一种用于形成传感器的方法，包括在衬底中形成通道，在通道中形成牺牲层，形成具有设置在衬底上的第一介电层的传感器，设置在第一电介质层上的石墨烯层，以及设置在第二电介质层 在石墨烯层上，源区域，漏极区域和栅极区域，其中栅极区域设置在牺牲层上，从沟道去除牺牲层。

    Stringer-free gate electrode for a suspended semiconductor fin
    87.
    发明授权
    Stringer-free gate electrode for a suspended semiconductor fin 有权
    一种用于悬浮半导体鳍片的无栅极栅电极

    公开(公告)号：US09029213B2

    公开(公告)日：2015-05-12

    申请号：US13891873

    申请日：2013-05-10

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey N. Sleight

    IPC: H01L21/77 ,  H01L29/78 ,  H01L29/66 ,  H01L29/775

    CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

    Abstract: At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin.

    Abstract translation: 在绝缘体层上形成至少一个半导体鳍片。 绝缘体层的一部分从至少一个半导体鳍片的下方蚀刻。 选择绝缘体的蚀刻部分的量使得金属栅极电极层填充绝缘体层的凹陷表面与至少一个半导体鳍片的底表面之间的整个间隙。 金属栅极电极层和半导体栅极电极层之间的界面在该至少一个半导体鳍片上连续地延伸，并且不在至少一个半导体鳍片的任何一个之下。 在栅电极的图形化期间，由于半导体栅极电极层不存在于至少一个半导体鳍片之下，所以能够促进半导体栅极电极层中的半导体材料的去除。

    Tapered fin field effect transistor
    88.
    发明授权
    Tapered fin field effect transistor 有权
    锥形场效应晶体管

    公开(公告)号：US09018084B2

    公开(公告)日：2015-04-28

    申请号：US14021165

    申请日：2013-09-09

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Ryan M. Martin ,  Jeffrey W. Sleight

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306

    CPC classification number: H01L29/7853 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/66795 ,  Y02P80/30

    Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.

    Abstract translation: 可以使用锥形鳍式场效应晶体管来提供通道的增强的静电控制。 在绝缘体层上形成具有基本上垂直的侧壁表面的半导体鳍片和介电鳍片盖的叠层。 半导体鳍片的侧壁表面被具有锥形厚度轮廓的介电翅片帽的蚀刻残余物材料钝化，使得蚀刻残余物质的厚度随着与介电翅片盖的距离而减小。 使用包括各向同性蚀刻部件的蚀刻来去除蚀刻残留物并且物理地暴露半导体鳍片的侧壁的下部。 蚀刻横向蚀刻半导体鳍片并在底部形成锥形区域。 半导体鳍片的底部的减小的横向宽度允许更好地控制鳍状场效应晶体管的沟道。

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