公开(公告)号：US10067886B2

公开(公告)日：2018-09-04

申请号：US15807187

申请日：2017-11-08

Applicant: International Business Machines Corporation

Inventor： Brian J. Connolly ,  Joab D. Henderson ,  Jeffrey A. Sabrowski ,  Saravanan Sethuraman ,  Kenneth L. Wright

IPC: G06F12/14 ,  G06F21/79

Abstract: This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.

公开(公告)号：US10057276B2

公开(公告)日：2018-08-21

申请号：US15268897

申请日：2016-09-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Saritha Arunkumar ,  Diyanesh B. Chinnakkonda Vidyapoornachary ,  Saravanan Sethuraman

IPC: H04L29/06 ,  G06F17/30

CPC classification number: H04L63/107 ,  G06F16/29 ,  G06F16/951 ,  H04L63/06 ,  H04L63/10 ,  H04L67/10 ,  H04W4/023 ,  H04W12/00503 ,  H04W12/04 ,  H04W12/06 ,  H04W12/08

Abstract: A method, computer program product, and system for authenticating a computing device by geographic attestation includes a processor utilizing executing an authentication application utilizing location services executing on the computing device to obtain location data from the location services. The processor obtains the location data and creates and encodes a data structure in a secured area of a memory; the data structure is only accessible to the authentication application. The processor transmits to an authentication server, an authentication request that includes the encoded location data, requesting access to secure content. The processor obtains a request to query identifiers proximate to the computing device for additional location information and queries the identifiers and transmits this additional location information to the authentication server. The processor receives a notification and based on obtaining the notification, erases the secured area and turns off the location services on the computing device.

公开(公告)号：US10042726B2

公开(公告)日：2018-08-07

申请号：US15841798

申请日：2017-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kyu-Hyoun Kim ,  Warren E. Maule ,  Kevin M. Mcilvain ,  Saravanan Sethuraman

IPC: G11C7/10 ,  G06F11/20

Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.

公开(公告)号：US09996411B1

公开(公告)日：2018-06-12

申请号：US15362912

申请日：2016-11-29

Applicant: International Business Machines Corporation

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Saravanan Sethuraman

IPC: G06F11/14 ,  G06F11/07 ,  G11C11/4096

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/14 ,  G11C11/4096

Abstract: Embodiments of the present invention provide methods, program products, and systems for improving DIMM level memory mirroring. Embodiments of the present invention can be used to configure a first memory module device of a pair memory module devices to receive a set of read and write operations and configure a second memory module device of the pair of memory module devices to receive only write operations of the set of read and write operations. Embodiments of the present invention can, responsive to detecting a failure, reconfiguring the first and the second memory module device to set the first memory module device to receive only write operations of the set of read and write operations and the second memory module device to receive read and write operations of the set of read and write operations.

公开(公告)号：US20180151246A1

公开(公告)日：2018-05-31

申请号：US15362935

申请日：2016-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Janani Mukundan ,  Karthick Rajamani ,  Saravanan Sethuraman

IPC: G11C29/12 ,  G11C11/16

CPC classification number: G11C29/12 ,  G11C11/1673 ,  G11C11/1675 ,  G11C14/0036 ,  G11C29/12005 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/52 ,  G11C2029/0401 ,  G11C2029/5004

Abstract: Examples of techniques for a built-in self-test (BIST) for embedded spin-transfer torque magnetic random access memory (STT-MRAM) are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: initiating, by a processor, a BIST for the STT-MRAM; performing, by the processor, an error-correcting code (ECC) test for a portion of the STT-MRAM; responsive to the ECC test not being passed, determining whether a maximum signal is reached; responsive to the maximum signal not being reached, increasing the signal and performing the ECC test again; and responsive to the maximum signal being reached, determining that the portion of the STT-MRAM is bad.

公开(公告)号：US09972376B2

公开(公告)日：2018-05-15

申请号：US14074171

申请日：2013-11-07

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  Carlos A. Fernandez ,  Joab D. Henderson ,  William P. Hovis ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

IPC: G11C11/406

CPC classification number: G11C11/40603 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

Abstract: A refresh command is received from a memory controller. An interruptible refresh containing multiple segment refreshes is initiated. The segment refreshes are separated by interrupt boundaries. A command is received before execution of a segment refresh. The first command is executed and execution of the first segment refresh is delayed at a first interrupt boundary. Alternatively, a first number of segment refreshes to execute is received from a memory controller. The received first number of segment refreshes is executed. A second number of segment refreshes to execute is received from a memory controller. The received second number of segment refreshes is executed. No segment refreshes are executed between the execution of the first number of segment refreshes and the execution of the second number of segment refreshes.

公开(公告)号：US09965017B2

公开(公告)日：2018-05-08

申请号：US15096599

申请日：2016-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Kyu-hyoun Kim ,  Saravanan Sethuraman ,  Gary A. Tressler

IPC: G06F1/32 ,  G06F1/26 ,  G06F3/06

CPC classification number: G06F1/3225 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3253 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0688

Abstract: A computer-implemented method for controlling power consumption in a non-volatile dual inline memory module (NVDIMM-N) may include determining, via a processor, whether the NVDIMM-N is receiving power from a main power source, inactivating, via the processor, a data bus connected to an NVDIMM-N memory group responsive to determining that the NVDIMM-N is not receiving power from the main power source, backing up data stored in the NVDIMM-N memory group, via the processor, to a non-volatile memory module integrated with the NVDIMM-N, where an NVDIMM-N controller can access the NVDIMM-N memory group while backing up, and transmitting, via the processor, a low power command to an NVDIMM-N controller to place the NVDIMM-N memory group in a low power mode.

公开(公告)号：US09921623B2

公开(公告)日：2018-03-20

申请号：US14696412

申请日：2015-04-25

Applicant: International Business Machines Corporation

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Edgar R. Cordero ,  Saravanan Sethuraman

IPC: G06F1/20 ,  G05D23/19 ,  H05K7/20

CPC classification number: G06F1/206 ,  G05D23/1928 ,  G05D23/1932 ,  H05K7/20145 ,  H05K7/20727

Abstract: A method, system and computer program product for implementing thermal air flow control management of a computer system. A temperature profile of the server system is identified. One or more dual in-line memory-modules (DIMMs) are used to pivot on an axis to direct air flow to cool identified hot spots based upon the temperature profile of the server system.

公开(公告)号：US09875034B2

公开(公告)日：2018-01-23

申请号：US15093243

申请日：2016-04-07

Applicant: International Business Machines Corporation

Inventor： Saravanan Sethuraman ,  Gary A Tressler ,  Harish Venkataraman

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G11C16/32 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/2209 ,  G11C2211/5623 ,  G11C2211/5642

Abstract: Embodiments herein describe a memory system that queues program requests to a block of flash memory until a predefined threshold is reached. That is, instead of performing program requests to write data into the block as the requests are received, the memory system queues the requests until the threshold is satisfied. Once the buffer for the block includes the threshold amount of program requests, the memory system performs the stored requests. In one embodiment, the memory system erases all the pages in the block before writing the new data in the program requests into the destination pages. The data that was originally stored in the pages that are not destination pages is rewritten into the pages. In this example, the queued program requests can be written into the pages using one erase and write step rather than individual erase and write steps for each of the requests.

公开(公告)号：US09710381B2

公开(公告)日：2017-07-18

申请号：US14307648

申请日：2014-06-18

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  David M. Daly ,  Robert K. Montoye ,  Saravanan Sethuraman ,  Diyanesh B. Chinnakkonda Vidyapoornachary

IPC: G06F12/08 ,  G06F9/50 ,  G06F12/0811 ,  G06F13/16 ,  G06F13/40 ,  G06F9/455 ,  G06F12/0831 ,  G06F3/00

CPC classification number: G06F12/0811 ,  G06F3/00 ,  G06F9/45558 ,  G06F9/50 ,  G06F12/0833 ,  G06F13/1673 ,  G06F13/4045 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/62

Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.