公开(公告)号：US20180114863A1

公开(公告)日：2018-04-26

申请号：US15846445

申请日：2017-12-19

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Kangguo Cheng ,  Zheng Xu

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/417 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate. A buffer layer is formed on a surface of the substrate between the first and second semiconductor fins and a semiconducting layer is formed on the buffer layer. The buffer layer is selectively removed and replaced with a dielectric layer. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a second channel region of the first semiconductor fin. Source and drain epitaxy regions are selectively formed on surfaces of the first gate.

公开(公告)号：US20180083092A1

公开(公告)日：2018-03-22

申请号：US15477296

申请日：2017-04-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Dongbing Shao ,  Zheng Xu

IPC: H01L49/02

CPC classification number: H01L28/92 ,  H01L28/40 ,  H01L28/60

Abstract: A capacitive device includes a first electrode comprising a nanosheet stack and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact is arranged on a basal end of the second electrode.

公开(公告)号：US20150348919A1

公开(公告)日：2015-12-03

申请号：US14823113

申请日：2015-08-11

Applicant: International Business Machines Corporation

Inventor： Pinping Sun ,  Chengwen Pei ,  Zheng Xu

IPC: H01L23/64 ,  H01L23/60 ,  H01F41/04

CPC classification number: H01F27/362 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/2871 ,  H01F27/289 ,  H01F41/041 ,  H01F2017/008 ,  H01F2027/2809 ,  H01L23/60 ,  H01L23/645 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure. A second ground shielding structure located within the second metal layer is electrically isolated from and circumferentially bounds the second inductor structure, whereby the first and second inductor generate a first inductance value based on the first ground shielding structure and second ground shielding structure being coupled to ground, and the first and second inductor generate a second inductance value based on the first ground shielding structure and second ground shielding structure electrically floating.

公开(公告)号：US20240348257A1

公开(公告)日：2024-10-17

申请号：US18301200

申请日：2023-04-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bodhisatwa Sadhu ,  Herschel Akiba Ainspan ,  Zheng Xu ,  Armagan Dascurcu ,  Gary Kurtzman

IPC: H03L7/18 ,  H03B5/12

CPC classification number: H03L7/18 ,  H03B5/1228 ,  H03B5/1296

Abstract: A Voltage-Controlled Oscillator (VCO) includes a cross-coupled transconductance cell. A transformer comprising a primary coil and at least one secondary coil, wherein the primary coil is connected to the cross-coupled transconductance cell. A primary coil varactor is connected to the cross-coupled transconductance cell in parallel to the primary coil. A variable inductive tuning component connected to the at least one secondary coil. A mode switch connected to the at least one secondary coil and configured to select a frequency mode of operation of the VCO by engaging or disengaging the variable inductive tuning component from operation with the primary coil varactor to generate oscillation at a center frequency of the VCO.

公开(公告)号：US11894303B2

公开(公告)日：2024-02-06

申请号：US17130164

申请日：2020-12-22

Applicant: International Business Machines Corporation

Inventor： Dongbing Shao ,  Chen Zhang ,  Zheng Xu ,  Tenko Yamashita

IPC: H01L23/528 ,  H01L21/822 ,  H01L23/50 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H10B41/20 ,  H10B51/20

CPC classification number: H01L23/5286 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/50 ,  H01L27/092 ,  H10B41/20 ,  H10B51/20

Abstract: A semiconductor structure includes a three-dimensional stacked transistor structure including first and second field-effect transistors of a first type at a first vertical level and third and fourth field-effect transistors of a second type at a second vertical level disposed over the first vertical level. The semiconductor structure also includes a first gate structure shared between the first and second field-effect transistors at the first vertical level, a second gate structure shared between the third and fourth field-effect transistors at the second vertical level, and a gate contact shared by the first and second gate structures. The wherein the first and second gate structures are vertically aligned with another in a layout of the three-dimensional stacked transistor structure between source drain/regions of the first, second, third and fourth field-effect transistors.

公开(公告)号：US11749529B2

公开(公告)日：2023-09-05

申请号：US17677469

申请日：2022-02-22

Applicant: International Business Machines Corporation

Inventor： Rasit Onur Topaloglu ,  Kafai Lai ,  Dongbing Shao ,  Zheng Xu

IPC: H01L21/033 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

公开(公告)号：US11665987B2

公开(公告)日：2023-05-30

申请号：US17192223

申请日：2021-03-04

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Dexin Kong ,  Zheng Xu

IPC: H10N70/00 ,  G11C13/00

CPC classification number: H10N70/8413 ,  G11C13/0004 ,  H10B63/30 ,  H10N70/023 ,  H10N70/063 ,  H10N70/068 ,  H10N70/231 ,  H10N70/881 ,  G11C2013/008

Abstract: An approach to form a semiconductor structure with a multiple layer phase change material stack and four electrodes that functions as an integrated switch device. The semiconductor structure includes a sidewall spacer that is on two opposing sides of the multiple layer phase change material stack contacting an edge of each layer of the multiple layer phase change material stack. The semiconductor structure includes a pair of a first type of electrode, where each of the pair of the first type of electrode abuts each of the sidewall spacers on the two opposing sides of the multiple layer phase change material stack. A pair of a second type of electrode, where each of the second type of electrode abuts each of two other opposing sides of the multiple layer phase change material stack and contacts a heater material on outside portions of the multiple layer phase change material stack.

公开(公告)号：US11362093B2

公开(公告)日：2022-06-14

申请号：US17037972

申请日：2020-09-30

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Zheng Xu ,  Dexin Kong ,  Kangguo Cheng

IPC: H01L23/52 ,  H01L27/105 ,  H01L21/8229 ,  H01L29/06

Abstract: A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps.

公开(公告)号：US11036126B2

公开(公告)日：2021-06-15

申请号：US16441911

申请日：2019-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chieh-Yu Lin ,  Dongbing Shao ,  Kehan Tian ,  Zheng Xu

IPC: G06F30/33 ,  G03F1/36 ,  G03F1/70 ,  G03F1/38 ,  G06F30/20 ,  G06F30/398 ,  G06F119/18

Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.

公开(公告)号：US10936782B2

公开(公告)日：2021-03-02

申请号：US16682365

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dongbing Shao ,  Zheng Xu ,  Lawrence A. Clevenger

IPC: G06F9/455 ,  G06F7/50 ,  G06F30/394 ,  G06F30/398 ,  G06F111/04 ,  G06F111/20

Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.