公开(公告)号：US08471356B2

公开(公告)日：2013-06-25

申请号：US12761780

申请日：2010-04-16

申请人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

发明人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC分类号： G06F17/50 ,  H01L21/768 ,  H01L23/525

CPC分类号： H01L23/5252 ,  G06F17/505 ,  H01L2924/0002 ,  H01L2924/00

摘要： Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

摘要翻译： 提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。 在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。 至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。 电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。 当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。

公开(公告)号：US20130134546A1

公开(公告)日：2013-05-30

申请号：US13307608

申请日：2011-11-30

申请人： Kangguo Cheng ,  Arjang Hassibi ,  Ali Khakifirooz ,  Dharmendra S. Modha

发明人： Kangguo Cheng ,  Arjang Hassibi ,  Ali Khakifirooz ,  Dharmendra S. Modha

IPC分类号： H01L27/12 ,  H01L21/28

CPC分类号： H01L27/1203 ,  A61B5/04001 ,  A61B2562/028 ,  A61B2562/046 ,  H01L21/76898

摘要： A method includes forming one or more trenches in a substrate; lining the one or more trenches with a dielectric liner; filling the one or more trenches with a conductive electrode to form one or more trench electrodes; forming a transistor layer on the substrate; connecting each of the one or more trench electrodes to at least one access transistor in the transistor layer; and thinning the substrate to expose at least a portion of each of the trench electrodes.

摘要翻译： 一种方法包括在衬底中形成一个或多个沟槽; 用介电衬垫衬一个或多个沟槽; 用导电电极填充一个或多个沟槽以形成一个或多个沟槽电极; 在所述基板上形成晶体管层; 将所述一个或多个沟槽电极中的每一个连接到所述晶体管层中的至少一个存取晶体管; 以及使基板变薄以暴露每个沟槽电极的至少一部分。

公开(公告)号：US20130134513A1

公开(公告)日：2013-05-30

申请号：US13307931

申请日：2011-11-30

申请人： Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Soon-Cheon Seo ,  Tenko Yamashita

发明人： Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Soon-Cheon Seo ,  Tenko Yamashita

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/6681 ,  H01L29/785

摘要： A FinFET with improved gate planarity and method of fabrication is disclosed. The gate is disposed on a pattern of fins prior to removing any unwanted fins. Lithographic techniques or etching techniques or a combination of both may be used to remove the unwanted fins. All or some of the remaining fins may be merged.

摘要翻译： 公开了一种具有改善的栅极平面度和制造方法的FinFET。 在移除任何不需要的翅片之前，门被设置在翅片图案上。 可以使用平版印刷技术或蚀刻技术或两者的组合来去除不需要的鳍片。 所有或一些剩余的翅片可能被合并。

公开(公告)号：US08420464B2

公开(公告)日：2013-04-16

申请号：US13100589

申请日：2011-05-04

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Sivananda K. Kanakasabapathy ,  Hemant Adhikari

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Sivananda K. Kanakasabapathy ,  Hemant Adhikari

IPC分类号： H01L21/8238

CPC分类号： H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

摘要： A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.

摘要翻译： 一种制造半导体器件的方法，其包括至少两个翅片结构，其中所述至少两个翅片结构中的一个包括外延形成的原位掺杂的第二源极和漏极区域，其具有存在于鳍的侧壁上的刻面外侧壁 结构体。 在另一个实施例中，本发明还提供一种制造finFET的方法，其包括在鳍结构的侧壁中形成凹槽，并且在形成在鳍结构中的凹槽中外延形成延伸掺杂区域。 还描述了通过上述方法形成的结构。

公开(公告)号：US20130082328A1

公开(公告)日：2013-04-04

申请号：US13251783

申请日：2011-10-03

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78654

摘要： Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.

摘要翻译： 公开了包括应激源的晶体管器件。 一个这样的晶体管器件包括沟道区，电介质层和半导体衬底。 沟道区域被配置为在源极区域和漏极区域之间提供导电沟道。 此外，电介质层在沟道区下方，并被配置为使沟道区电绝缘。 此外，半导体衬底在沟道区域下方和介电层下方包括在半导体衬底的顶表面处的位错缺陷，其中位错缺陷共同定向以在沟道区域施加压缩应变，使得载流子 渠道区域的移动性得到增强。

公开(公告)号：US20130071979A1

公开(公告)日：2013-03-21

申请号：US13606382

申请日：2012-09-07

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

IPC分类号： H01L21/336

CPC分类号： H01L29/41783 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78654

摘要： A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.

摘要翻译： 一种用于制造场效应晶体管器件的方法，包括在衬底上形成栅极叠层，在衬底上邻近栅堆叠形成间隔物，在衬底上形成有源区的第一部分，有源区的第一部分 具有邻近所述栅叠层的第一刻面，在所述有源区的所述第一部分的一部分上形成所述有源区的第二部分，所述有源区的所述第二部分具有邻近所述栅叠层的第二刻面， 第一小面表面和第二小面表面部分地限定与栅极叠层相邻的空腔。

公开(公告)号：US08367544B2

公开(公告)日：2013-02-05

申请号：US12582137

申请日：2009-10-20

申请人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

IPC分类号： H01L21/44

CPC分类号： H01L21/76808 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76829

摘要： A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.

摘要翻译： 形成半导体器件的方法包括：图案化在待蚀刻的均匀半导体器件层上形成的光致抗蚀剂层; 对半导体器件进行注入工艺，该注入工艺根据待均匀半导体器件层内待蚀刻的特征的位置以及在要蚀刻的特征的期望深度选择性地埋入自对准的牺牲蚀刻停止层; 将由图案化的光致抗蚀剂层限定的特征图案蚀刻成均匀的半导体器件层，停止在注入的牺牲蚀刻停止层上; 以及在用填充材料填充蚀刻的特征图案之前去除注入的牺牲蚀刻停止层的剩余部分。

公开(公告)号：US08343877B2

公开(公告)日：2013-01-01

申请号：US12614952

申请日：2009-11-09

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L21/302

CPC分类号： H01L21/28132 ,  H01L21/26586 ,  H01L29/66787

摘要： A method for fabrication of features of an integrated circuit and device thereof include patterning a first structure on a surface of a semiconductor device and forming spacers about a periphery of the first structure. An angled ion implantation is applied to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions. The unprotected portions and the first structure are selectively removed with respect to the protected portions. A layer below the protected portions of the spacer is patterned to form integrated circuit features.

摘要翻译： 一种用于制造集成电路的特征的方法及其装置包括在半导体器件的表面上形成第一结构并在第一结构的周围形成间隔物。 将角度离子注入施加到器件，使得间隔物具有来自成角度离子注入的保护部分和未受保护部分，其中未保护部分具有大于被保护部分的蚀刻速率的蚀刻速率。 相对于受保护部分，非保护部分和第一结构被选择性地去除。 将间隔物的受保护部分下面的层图案化以形成集成电路特征。

公开(公告)号：US08338260B2

公开(公告)日：2012-12-25

申请号：US12760250

申请日：2010-04-14

申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam Shahidi

发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam Shahidi

IPC分类号： H01L21/336

CPC分类号： H01L29/78654 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/78618

摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.

摘要翻译： 提供一种晶体管，其包括衬底上方的掩埋氧化物层。 硅层在掩埋氧化物层之上。 栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。 氮化物衬垫与栅堆叠相邻。 氧化物衬垫与氮化物衬垫相邻。 一组具有包括硅层的一部分的部分的凸起的源/漏区。 所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

公开(公告)号：US20120322251A1

公开(公告)日：2012-12-20

申请号：US13597331

申请日：2012-08-29

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

IPC分类号： H01L21/28

CPC分类号： H01L29/42364 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： In one exemplary embodiment of the invention, a method (e.g., to fabricate a semiconductor device having a borderless contact) including: forming a first gate structure on a substrate; depositing an interlevel dielectric over the first gate structure; planarizing the interlevel dielectric to expose a top surface of the first gate structure; removing at least a portion of the first gate structure; forming a second gate structure in place of the first gate structure; forming a contact area for the borderless contact by removing a portion of the interlevel dielectric; and forming the borderless contact by filling the contact area with a metal-containing material.

摘要翻译： 在本发明的一个示例性实施例中，一种方法（例如，制造具有无边界接触的半导体器件）包括：在衬底上形成第一栅极结构; 在所述第一栅极结构上沉积层间电介质; 平面化所述层间电介质以暴露所述第一栅极结构的顶表面; 去除所述第一栅极结构的至少一部分; 形成第二栅极结构来代替第一栅极结构; 通过去除所述层间电介质的一部分来形成所述无边界接触的接触区域; 以及通过用含金属材料填充接触区域来形成无边界接触。