公开(公告)号：US10409506B2

公开(公告)日：2019-09-10

申请号：US16117348

申请日：2018-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F12/0804 ,  G06F13/28 ,  G06F12/0846

Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.

公开(公告)号：US10248500B2

公开(公告)日：2019-04-02

申请号：US15267844

申请日：2016-09-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Mark A. Helm ,  Aaron S. Yip

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26 ,  G11C29/52 ,  H03M13/11 ,  H03M13/37 ,  H03M13/00 ,  G11C29/04 ,  H03M13/29

Abstract: Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense operation to detect first memory cells of the plurality of memory cells that stored charge sufficiently above a transition voltage threshold where the first memory cells are unlikely to be erroneous. The sense circuit further performs a fine sense operation to sense second memory cells of the plurality of memory cells having stored charge near the transition voltage between adjacent logic states. The first memory cells remain unsensed during the fine sense operation. The second memory cells detected during the fine sense operation may have an increased likelihood of being erroneous. Responsive to a number of sensed second memory cells near the transition voltage exceeding a threshold, additional sensing operations are performed by the sense circuit.

公开(公告)号：US09519582B2

公开(公告)日：2016-12-13

申请号：US14833175

申请日：2015-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC: G06F12/00 ,  G06F12/08 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

公开(公告)号：US20160099048A1

公开(公告)日：2016-04-07

申请号：US14868604

申请日：2015-09-29

Applicant: Micron Technology, Inc.

Inventor： Qiang Tang ,  Feng Pan ,  Ramin Ghodsi ,  Mark A. Helm

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G11C7/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.

Abstract translation: 描述了用于阈值电压（Vt）分布测定的装置和方法。 许多设备可以包括感测电路，其被配置为确定存储器单元阵列的源极线上的第一电流，第一电流对应于响应于第一感测而导通的一组存储器单元的第一数量的存储器单元 施加到访问线路的电压并确定源极线路上的第二电流，第二电流对应于响应于施加到接入线路的第二感测电压而导通的组中的第二数量的存储器单元。 设备的数量可以包括控制器，其被配置为至少部分地基于第一电流和第二电流来确定对应于该组存储器单元的Vt分布的至少一部分。

公开(公告)号：US20150262695A1

公开(公告)日：2015-09-17

申请号：US14724065

申请日：2015-05-28

Applicant: Micron Technology, Inc.

Inventor： Mark A. Helm ,  Uday Chandrasekhar

IPC: G11C16/28 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C16/28 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G11C16/3454 ,  G11C29/52 ,  H03M13/03 ,  H03M13/05

Abstract: The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.

Abstract translation: 本公开包括用于数据感测的方法和装置。 一种这样的方法包括使用多个不同感测电压对多个存储器单元执行多个连续感测操作，确定在连续感测操作的数量的连续感测操作之间改变状态的数量存储器单元的数量，以及确定 至少部分地基于确定在连续感测操作之间改变状态的存储器单元的数量的确定数量，是否输出对应于多个连续感测操作中的一个的硬数据。

公开(公告)号：US20150228659A1

公开(公告)日：2015-08-13

申请号：US14175901

申请日：2014-02-07

Applicant: Micron Technology, Inc.

Inventor： Luyen Vu ,  Mark A. Helm

IPC: H01L27/115 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L29/16

Abstract: Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).

Abstract translation: 一些实施例包括具有基本上六边形最紧密堆积布置的半导体柱的装置。 六边形最紧密的包装布置包括具有7个不同支柱的至少部分的重复支柱图案。 重复柱图案中的相应一个中的每个不同的支柱能够电耦合到多条数据线的不同数据线。 一些实施例包括具有基本上六边形最紧密堆积布置的半导体柱的装置。 六边形最接近的包装布置包括具有7个不同柱的至少一部分的重复柱图形。 重复柱状图案的所有7个不同的柱由单个排水侧选择栅（SGD）包围。

公开(公告)号：US20150194218A1

公开(公告)日：2015-07-09

申请号：US14663179

申请日：2015-03-19

Applicant: Micron Technology, Inc.

Inventor： Matthew Goldman ,  Pranav Kalavade ,  Uday Chandrasekhar ,  Mark A. Helm

IPC: G11C16/28 ,  G06F12/08 ,  G11C16/04

CPC classification number: G11C16/28 ,  G06F12/0875 ,  G06F2212/452 ,  G11C16/04 ,  G11C16/26 ,  G11C16/3427

Abstract: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.

Abstract translation: 本公开涉及存储器单元感测。 一种或多种方法包括确定耦合到第一数据线的第一存储器单元的数据状态，确定耦合到第三数据线的第三存储器单元的数据状态，传送第一和第三数据线中的至少一个的确定数据 存储单元连接到与第二存储器单元耦合的第二数据线相对应的数据线控制单元，第二数据线与第一数据线和第三数据线相邻，并且确定第二存储器单元的数据状态 至少部分地基于所转移的确定的数据。