公开(公告)号：US09368202B2

公开(公告)日：2016-06-14

申请号：US14713878

申请日：2015-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Vimercati ,  Riccardo Muzzetto

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/12 ,  G11C8/08 ,  G11C7/14 ,  G11C7/06 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0052 ,  G11C2013/0054 ,  G11C2029/0409 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2207/063 ,  G11C2213/79

Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.

公开(公告)号：US20150279459A1

公开(公告)日：2015-10-01

申请号：US14740074

申请日：2015-06-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Vimercati ,  Riccardo Muzzetto

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/02 ,  G11C7/04 ,  G11C7/14 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory device, can determine a value of a data digit, such as a bit, stored in a non-volatile memory cell based at least partly on the reference current. The reference current can be generated by mirroring a current at a node that is biased by a voltage bias. A configurable resistance circuit can have a resistance that is configurable. The resistance of the configurable resistance circuit can be in series between the node and a resistive non-volatile memory element. In some embodiments, a plurality of non-volatile memory elements can each be electrically connected in series between the resistance of the configurable resistance circuit and a corresponding selector.

公开(公告)号：US20150200007A1

公开(公告)日：2015-07-16

申请号：US14668812

申请日：2015-03-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gerald John Barkley ,  Daniele Vimercati ,  Pierguido Garofalo

IPC: G11C13/00 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C5/025 ,  G11C7/1042 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.

Abstract translation: 本文公开的主题涉及方法和装置，诸如包括这种存储装置的存储装置和系统。 在一个装置示例中，可以采用多个块配置。 块配置可以包括类似掺杂的半导体开关的布置。 块配置可以选择存储器阵列的相应瓦片，相应瓦片的特定存储器单元，并且选择应用于特定存储器单元的存储器操作。 存储器阵列的特定切片内的紧邻相邻的块配置可以基本上镜像，并且在存储器阵列的分离的紧邻相邻切片中的紧密相邻的块配置可以基本相似。 用于基本上镜像的块配置的类似掺杂的半导体开关的类似的掺杂扩散区可以被布置成电共享公共的电位信号值电平。 还公开了其它装置和方法。

公开(公告)号：US08817554B2

公开(公告)日：2014-08-26

申请号：US14068724

申请日：2013-10-31

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C7/06

CPC classification number: G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  H03F3/45762 ,  H03F2200/261 ,  H03F2203/45536 ,  H03F2203/45544 ,  H03F2203/45551

Abstract: Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances.

Abstract translation: 公开了用于感测存储器单元的数据状态的感测放大器，存储器以及装置和方法。 示例性装置包括：差分放大器，被配置为放大施加到第一和第二放大器输入节点的电压之间的电压差以提供输出。 该示例设备还包括耦合到第一和第二放大器输入节点的第一和第二电容。 耦合到第一和第二电容的开关块被配置为在参考输入节点的第一阶段期间将第一和第二电容耦合到第一放大器输入节点。 开关块还被配置为在第一阶段期间将放大器的输出耦合到第二放大器输入节点以建立补偿条件。 在第二阶段期间，开关块将其输入节点耦合到第一和第二电容。

公开(公告)号：US20250037756A1

公开(公告)日：2025-01-30

申请号：US18791706

申请日：2024-08-01

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Daniele Vimercati

IPC: G11C11/4091 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

公开(公告)号：US12073870B2

公开(公告)日：2024-08-27

申请号：US18217205

申请日：2023-06-30

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Daniele Vimercati

IPC: G11C7/06 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

公开(公告)号：US12069847B2

公开(公告)日：2024-08-20

申请号：US18133929

申请日：2023-04-12

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/24 ,  G11C11/22 ,  G11C11/408 ,  H01L27/06 ,  H01L29/786 ,  H10B12/00 ,  H10B53/20

CPC classification number: H10B12/30 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/408 ,  H01L27/0688 ,  H01L29/78642 ,  H10B53/20

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

公开(公告)号：US11837269B2

公开(公告)日：2023-12-05

申请号：US17462213

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22 ,  G11C11/4096 ,  G11C11/4091

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/4091 ,  G11C11/4096

Abstract: Methods, systems, and devices for deck-level signal development cascodes are described. A memory device may include transistors that support both a signal development and decoding functionality. In a first operating condition (e.g., an open-circuit condition), a transistor may be operable to isolate first and second portions of an access line based on a first voltage applied to a gate of the transistor. In a second operating condition (e.g., a signal development condition), the transistor may be operable to couple the first and second portions of the access line and generate an access signal based on a second voltage applied to the gate of the transistor. In a third operating condition (e.g., a closed-circuit condition), the transistor may be operable to couple the first and second portions of the access line based on applying a third voltage greater than the second voltage to the gate of the transistor.

公开(公告)号：US20230368831A1

公开(公告)日：2023-11-16

申请号：US17740528

申请日：2022-05-10

Applicant: Micron Technology, Inc.

Inventor： Makoto Kitagawa ,  Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2259 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275

Abstract: A method of performing a memory cell operation can include maintaining a plate voltage at a first access line of a memory cell during at least a first operation and a second operation of the memory cell. The method can further include charging a second access line to a first voltage greater than zero and greater than a threshold voltage of a selector device of the memory cell during the first operation on the memory cell. The method can further include, subsequent to the first operation, charging the second access line to a second voltage greater than the plate voltage plus the threshold voltage of the selector device to perform the second operation of the memory cell.

公开(公告)号：US11735249B2

公开(公告)日：2023-08-22

申请号：US17362306

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C5/063 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4096

Abstract: Methods, systems, and devices for sensing techniques for differential memory cells are described. A method may include selecting a pair of memory cells that comprise a first memory cell coupled with a first digit line and a second memory cell coupled with a second digit line for a read operation, the pair of memory cells storing one bit of information. The method may further include applying a first voltage to a plate line coupled with the first memory cell and the second memory cell and applying a second voltage to a select line to couple the first digit line and the second digit line with a sense amplifier. The amplifier may sense a logic state of the pair of memory cells based on a difference between a third voltage of the first digit line and a fourth voltage of the second digit line.