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    MEMS device integrated chip package, and method of making same
    81.
    发明授权
    MEMS device integrated chip package, and method of making same 有权
    MEMS器件集成芯片封装及其制造方法

    公开(公告)号：US07291561B2

    公开(公告)日：2007-11-06

    申请号：US10623965

    申请日：2003-07-21

    Applicant: Qing Ma ,  Peng Cheng ,  Valluri Rao

    Inventor： Qing Ma ,  Peng Cheng ,  Valluri Rao

    IPC: H01L21/461 ,  H01L21/311 ,  H01L29/00 ,  H01L27/108

    CPC classification number: B81C1/00333 ,  H01G5/16 ,  H01G5/40 ,  H01L2224/48091 ,  Y10T428/24248 ,  H01L2924/00014

    Abstract: The present invention relates to a chip package that includes a semiconductor device and at least one micro electromechanical structure (MEMS) such that the semiconductor device and the MEMS form an integrated package. One embodiment of the present invention includes a semiconductor device, a first MEMS device disposed in a conveyance such as a film, and a second MEMS device disposed upon the semiconductor device through a via in the conveyance.The present invention also relates to a process of forming a chip package that includes providing a conveyance such as a tape automated bonding (TAB) structure, that may hold at least one MEMS device. The method is further carried out by disposing the conveyance over the active surface of the device in a manner that causes the at least one MEMS to communicate electrically to the active surface. Where appropriate, a sealing structure such as a solder ring may be used to protect the MEMS.

    Abstract translation: 本发明涉及包括半导体器件和至少一个微机电结构（MEMS）的芯片封装，使得半导体器件和MEMS形成集成封装。 本发明的一个实施例包括半导体器件，设置在诸如膜的输送器中的第一MEMS器件，以及通过输送中的通孔设置在半导体器件上的第二MEMS器件。 本发明还涉及一种形成芯片封装的方法，其包括提供诸如胶带自动键合（TAB）结构的输送，其可以保持至少一个MEMS器件。 该方法进一步通过以使得至少一个MEMS与活性表面电连通的方式布置在器件的有效表面上的输送来进行。 在适当的情况下，可以使用诸如焊环的密封结构来保护MEMS。

    Fabrication of on-package and on-chip structure using build-up layer process
    83.
    发明授权
    Fabrication of on-package and on-chip structure using build-up layer process 有权
    使用堆积层工艺制造封装和片上结构

    公开(公告)号：US06890829B2

    公开(公告)日：2005-05-10

    申请号：US10246360

    申请日：2002-09-17

    Applicant: Peng Cheng ,  Qing Ma

    Inventor： Peng Cheng ,  Qing Ma

    IPC: H01L23/522 ,  H01L27/08 ,  H01L21/20

    CPC classification number: H01L23/5227 ,  H01L24/19 ,  H01L27/08 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/00

    Abstract: The invention relates to a process of forming an on-chip package inductor. The process includes providing a substrate with at least one microelectronic device packaged therewith. As part of the inventive process, electrical communication is formed for the microelectronic device. The electrical communication includes at least two electrically conductive layers. As part of the inventive technology, the inductor is patterned on the substrate before, during, or after formation of the electrical communication. The inductor is connected to the at least one microelectronic device.

    Abstract translation: 本发明涉及一种形成片上封装电感器的工艺。 该方法包括提供具有与其一起封装的至少一个微电子器件的衬底。 作为本发明方法的一部分，为微电子器件形成电通信。 电通信包括至少两个导电层。 作为本发明技术的一部分，电感器在形成电通信之前，期间或之后在衬底上图案化。 电感器连接到至少一个微电子器件。

    High dielectric constant metal oxide gate dielectrics
    84.
    发明申请
    High dielectric constant metal oxide gate dielectrics 失效
    高介电常数金属氧化物栅极电介质

    公开(公告)号：US20050087820A1

    公开(公告)日：2005-04-28

    申请号：US10646034

    申请日：2003-08-22

    Applicant: Gang Bai ,  David Fraser ,  Brian Doyle ,  Peng Cheng ,  Chunlin Liang

    Inventor： Gang Bai ,  David Fraser ,  Brian Doyle ,  Peng Cheng ,  Chunlin Liang

    IPC: H01L21/28 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/76

    CPC classification number: H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28229 ,  H01L29/517

    Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

    Abstract translation: 形成适合用作金属氧化物半导体场效应晶体管（MOSFET）的栅极电介质层的电介质层的方法包括氧化硅衬底的表面，在氧化表面上形成金属层，并使金属 与氧化表面形成超过衬底的基本上本征的硅层，其中硅层的至少一部分可以是外延硅层，以及位于硅层之上的金属氧化物层。 在本发明的另一方面，集成电路包括多个MOSFET，其中多个晶体管中的各个晶体管具有金属氧化物栅极电介质层和位于金属氧化物电介质层之下的基本上本征的硅层。

    MEMS device integrated chip package, and method of making same
    86.
    发明授权
    MEMS device integrated chip package, and method of making same 有权
    MEMS器件集成芯片封装及其制造方法

    公开(公告)号：US06621137B1

    公开(公告)日：2003-09-16

    申请号：US09687907

    申请日：2000-10-12

    Applicant: Qing Ma ,  Peng Cheng ,  Valluri Rao

    Inventor： Qing Ma ,  Peng Cheng ,  Valluri Rao

    IPC: H01L2900

    CPC classification number: B81C1/00333 ,  H01G5/16 ,  H01G5/40 ,  H01L2224/48091 ,  Y10T428/24248 ,  H01L2924/00014

    Abstract: The present invention relates to a chip package that includes a semiconductor device and at least one micro electromechanical structure (MEMS) such that the semiconductor device and the MEMS form an integrated package. One embodiment of the present invention includes a semiconductor device, a first MEMS device disposed in a conveyance such as a film, and a second MEMS device disposed upon the semiconductor device through a via in the conveyance. The present invention also relates to a process of forming a chip package that includes providing a conveyance such as a tape automated bonding (TAB) structure that may bold at least one MEMS device. The method is further carried out by disposing the conveyance over the active surface of the device in a manner that causes the at least one MEMS to communicate electrically to the active surface. Where appropriate, a sealing structure such as a solder ring may be used to protect the MEMS.

    Abstract translation: 本发明涉及包括半导体器件和至少一个微机电结构（MEMS）的芯片封装，使得半导体器件和MEMS形成集成封装。 本发明的一个实施例包括半导体器件，设置在诸如膜的输送器中的第一MEMS器件，以及通过输送中的通孔设置在半导体器件上的第二MEMS器件。 本发明还涉及一种形成芯片封装的方法，其包括提供输送，例如可以使至少一个MEMS器件粗化的带自动键合（TAB）结构。 该方法进一步通过以使得至少一个MEMS与活性表面电连通的方式布置在器件的有效表面上的输送来进行。 在适当的情况下，可以使用诸如焊环的密封结构来保护MEMS。

    Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer
    88.
    发明授权
    Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer 有权
    使用两个边缘限定层和间隔物在集成电路中制造特征的方法

    公开(公告)号：US06596609B2

    公开(公告)日：2003-07-22

    申请号：US09740782

    申请日：2000-12-19

    Applicant: Peng Cheng ,  Brian S. Doyle

    Inventor： Peng Cheng ,  Brian S. Doyle

    IPC: H01L21265

    CPC classification number: H01L21/28132 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  Y10S438/947

    Abstract: A method of fabricating a feature on a substrate is disclosed. In a described embodiment the feature is the gate electrode of an MOS transistor. In this embodiment a polysilicon layer is formed on the substrate. Next, an edge definition layer of silicon nitride is formed on the feature layer. Then, a patterned edge definition layer of silicon dioxide is formed on the first edge definition layer. Then, a silicon nitride spacer is formed adjacent to an edge of the patterned second edge definition layer. Finally, the polysilicon layer is etched, forming the transistor gate electrode from the polysilicon that remains under the spacer.

    Abstract translation: 公开了一种在衬底上制造特征的方法。 在所描述的实施例中，特征是MOS晶体管的栅电极。 在该实施例中，在衬底上形成多晶硅层。 接下来，在特征层上形成氮化硅的边缘限定层。 然后，在第一边缘限定层上形成图案化的二氧化硅边缘限定层。 然后，与图案化的第二边缘限定层的边缘相邻地形成氮化硅间隔物。 最后，蚀刻多晶硅层，从保留在间隔物下方的多晶硅形成晶体管栅电极。

    Resonator frequency correction by modifying support structures
    89.
    发明授权
    Resonator frequency correction by modifying support structures 有权
    谐振器频率校正通过修改支持结构

    公开(公告)号：US06570468B2

    公开(公告)日：2003-05-27

    申请号：US09895360

    申请日：2001-06-29

    Applicant: Qing Ma ,  Peng Cheng ,  Valluri R. Rao

    Inventor： Qing Ma ,  Peng Cheng ,  Valluri R. Rao

    IPC: H03H905

    CPC classification number: H03H3/0077 ,  H03H9/2463 ,  Y10S977/70 ,  Y10S977/721 ,  Y10S977/733 ,  Y10S977/888 ,  Y10S977/889

    Abstract: A method including to a resonator coupled to at least one support structure on a substrate, the resonator having a resonating frequency in response to a frequency stimulus, modifying the resonating frequency by modifying the at least one support structure. A method including forming a resonator coupled to at least one support structure on a chip-level substrate, the resonator having a resonating frequency; and modifying the resonating frequency of the resonator by modifying the at least one support structure. A method including applying a frequency stimulus to a resonator coupled to at least one support structure on a chip-level substrate determining a resonating frequency; and modifying the resonating frequency of the resonator by modifying the at least one support structure. An apparatus including a resonator coupled to at least one support structure on a chip-level substrate, the resonator having a resonating frequency tuned by the modification of the at least one support structure to a selected frequency stimulus.

    Abstract translation: 一种方法，包括耦合到衬底上的至少一个支撑结构的谐振器，所述谐振器响应于频率刺激具有谐振频率，通过修改所述至少一个支撑结构来修改谐振频率。 一种方法，包括形成耦合到芯片级衬底上的至少一个支撑结构的谐振器，所述谐振器具有谐振频率; 以及通过修改所述至少一个支撑结构来修改谐振器的谐振频率。 一种方法，包括对耦合到芯片级衬底上的至少一个支撑结构的谐振器施加频率刺激，确定谐振频率; 以及通过修改所述至少一个支撑结构来修改谐振器的谐振频率。 一种包括耦合到芯片级衬底上的至少一个支撑结构的谐振器的谐振器，所述谐振器具有通过所述至少一个支撑结构的修改调谐到所选择的频率刺激的谐振频率。

    High dielectric constant metal oxide gate dielectrics
    90.
    发明授权
    High dielectric constant metal oxide gate dielectrics 有权
    高介电常数金属氧化物栅极电介质

    公开(公告)号：US06528856B1

    公开(公告)日：2003-03-04

    申请号：US09212773

    申请日：1998-12-15

    Applicant: Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

    Inventor： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

    IPC: H01L2976

    CPC classification number: H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28229 ,  H01L29/517

    Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

    Abstract translation: 形成适合用作金属氧化物半导体场效应晶体管（MOSFET）的栅极电介质层的电介质层的方法包括氧化硅衬底的表面，在氧化表面上形成金属层，并使金属 与氧化表面形成超过衬底的基本上本征的硅层，其中硅层的至少一部分可以是外延硅层，以及位于硅层之上的金属氧化物层。 在本发明的另一方面，集成电路包括多个MOSFET，其中多个晶体管中的各个晶体管具有金属氧化物栅极电介质层和位于金属氧化物电介质层之下的基本上本征的硅层。

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