公开(公告)号：US20190035937A1

公开(公告)日：2019-01-31

申请号：US16024967

申请日：2018-07-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Tetsuhiro TANAKA ,  Hirokazu WATANABE ,  Yuhei SATO ,  Yasumasa YAMANE ,  Daisuke MATSUBAYASHI

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/45

Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

公开(公告)号：US20190027614A1

公开(公告)日：2019-01-24

申请号：US16126348

申请日：2018-09-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L27/105 ,  H01L29/04 ,  H01L27/146 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L27/1052 ,  H01L27/1225 ,  H01L27/14616 ,  H01L29/04 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7854 ,  H01L29/7869 ,  H01L29/78693

Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.

公开(公告)号：US20180158961A1

公开(公告)日：2018-06-07

申请号：US15828759

申请日：2017-12-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L27/105 ,  H01L29/04 ,  H01L27/146 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L27/1052 ,  H01L27/1225 ,  H01L27/14616 ,  H01L29/04 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7854 ,  H01L29/7869 ,  H01L29/78693

Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.

公开(公告)号：US20180151743A1

公开(公告)日：2018-05-31

申请号：US15865308

申请日：2018-01-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Akihisa SHIMOMURA ,  Yuhei SATO ,  Yasumasa YAMANE ,  Yoshitaka YAMAMOTO ,  Hideomi SUZAWA ,  Tetsuhiro TANAKA ,  Yutaka OKAZAKI ,  Naoki OKUNO ,  Takahisa ISHIYAMA

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/78606 ,  H01L29/78696

Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.

公开(公告)号：US20180026140A1

公开(公告)日：2018-01-25

申请号：US15704093

申请日：2017-09-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yoshinobu ASAMI ,  Yutaka OKAZAKI ,  Motomu KURATA ,  Katsuaki TOCHIBAYASHI ,  Shinya SASAGAWA ,  Kensuke YOSHIZUMI ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L21/477 ,  H01L21/4757 ,  H01L29/66 ,  H01L33/00 ,  H01L21/47

CPC classification number: H01L29/7869 ,  H01L21/47 ,  H01L21/4757 ,  H01L21/477 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78648 ,  H01L33/00

Abstract: A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.

公开(公告)号：US20170294453A1

公开(公告)日：2017-10-12

申请号：US15629970

申请日：2017-06-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

公开(公告)号：US20170278978A1

公开(公告)日：2017-09-28

申请号：US15618480

申请日：2017-06-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Yutaka OKAZAKI

IPC: H01L29/786 ,  H01L27/105 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78606 ,  H01L27/1052 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer filling a groove is surrounded by insulating layers including an aluminum oxide film containing excess oxygen. Excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer, in which a channel is formed, by heat treatment in a manufacturing process of the semiconductor device. Moreover, the aluminum oxide film forms a barrier against oxygen and hydrogen, which inhibits the removal of oxygen from the oxide semiconductor layer surrounded by the insulating layers including an aluminum oxide film and the entry of impurities such as hydrogen in the oxide semiconductor layer. Thus, a highly purified intrinsic oxide semiconductor layer can be obtained. The threshold voltage is controlled effectively by gate electrode layers formed over and under the oxide semiconductor layer.

公开(公告)号：US20170054030A1

公开(公告)日：2017-02-23

申请号：US15342316

申请日：2016-11-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/66969

Abstract: An object of an embodiment of the present invention is to provide a semiconductor device including a normally-off oxide semiconductor element whose characteristic variation is small in the long term. A cation containing one or more elements selected from oxygen and halogen is added to an oxide semiconductor layer, thereby suppressing elimination of oxygen, reducing hydrogen, or suppressing movement of hydrogen. Accordingly, carriers in the oxide semiconductor can be reduced and the number of the carriers can be kept constant in the long term. As a result, the semiconductor device including the normally-off oxide semiconductor element whose characteristic variation is small in the long term can be provided.

Abstract translation: 本发明的一个实施例的目的是提供一种包括其长期特性变化小的常关氧化物半导体元件的半导体器件。 将含有选自氧和卤素的一种或多种元素的阳离子加入到氧化物半导体层中，从而抑制氧的消除，还原氢或抑制氢的移动。 因此，可以减少氧化物半导体中的载流子，并且可以长期保持载流子的数量恒定。 结果，可以提供包括其长期特性变化小的常关氧化物半导体元件的半导体器件。

公开(公告)号：US20170005203A1

公开(公告)日：2017-01-05

申请号：US15192312

申请日：2016-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Sachiaki TEZUKA ,  Tetsuhiro TANAKA ,  Toshiya ENDO ,  Mitsuhiro ICHIJO

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78651 ,  H01L29/7869

Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.

Abstract translation: 提供了一种小型化的晶体管。 在半导体上的第三绝缘体上形成第一层; 在第一层上形成第二层; 在第二层上形成蚀刻掩模; 使用蚀刻掩模蚀刻第二层，直到第一层暴露以形成第三层; 选择性生长层形成在第三层的顶表面和侧表面上; 使用第三层和选择性生长层来蚀刻第一层，直到暴露第三绝缘体以形成第四层; 并且使用第三层，选择性生长层和第四层蚀刻第三绝缘体，直到半导体暴露以形成第一绝缘体。

公开(公告)号：US20160293768A1

公开(公告)日：2016-10-06

申请号：US15184213

申请日：2016-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Akihisa SHIMOMURA ,  Tetsuhiro TANAKA ,  Sachiaki TEZUKA

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/105 ,  H01L29/26 ,  H01L29/41733 ,  H01L29/78 ,  H01L29/78693 ,  H01L29/78696

Abstract: Disclosed is a semiconductor device including two oxide semiconductor layers, where one of the oxide semiconductor layers has an n-doped region while the other of the oxide semiconductor layers is substantially i-type. The semiconductor device includes the two oxide semiconductor layers sandwiched between a pair of oxide layers which have a common element included in any of the two oxide semiconductor layers. A double-well structure is formed in a region including the two oxide semiconductor layers and the pair of oxide layers, leading to the formation of a channel formation region in the n-doped region. This structure allows the channel formation region to be surrounded by an i-type oxide semiconductor, which contributes to the production of a semiconductor device that is capable of feeding enormous current.

Abstract translation: 公开了包括两个氧化物半导体层的半导体器件，其中氧化物半导体层中的一个具有n掺杂区域，而另一个氧化物半导体层基本上是i型。 半导体器件包括夹在一对氧化物层之间的两个氧化物半导体层，其具有包含在两个氧化物半导体层中的任一个中的共同元素。 在包括两个氧化物半导体层和一对氧化物层的区域中形成双阱结构，导致在n掺杂区域中形成沟道形成区域。 该结构允许沟道形成区域被i型氧化物半导体包围，这有助于生产能够馈送大量电流的半导体器件。