公开(公告)号：US20170005203A1

公开(公告)日：2017-01-05

申请号：US15192312

申请日：2016-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Sachiaki TEZUKA ,  Tetsuhiro TANAKA ,  Toshiya ENDO ,  Mitsuhiro ICHIJO

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78651 ,  H01L29/7869

Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.

Abstract translation: 提供了一种小型化的晶体管。 在半导体上的第三绝缘体上形成第一层; 在第一层上形成第二层; 在第二层上形成蚀刻掩模; 使用蚀刻掩模蚀刻第二层，直到第一层暴露以形成第三层; 选择性生长层形成在第三层的顶表面和侧表面上; 使用第三层和选择性生长层来蚀刻第一层，直到暴露第三绝缘体以形成第四层; 并且使用第三层，选择性生长层和第四层蚀刻第三绝缘体，直到半导体暴露以形成第一绝缘体。

公开(公告)号：US20160293768A1

公开(公告)日：2016-10-06

申请号：US15184213

申请日：2016-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Akihisa SHIMOMURA ,  Tetsuhiro TANAKA ,  Sachiaki TEZUKA

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/105 ,  H01L29/26 ,  H01L29/41733 ,  H01L29/78 ,  H01L29/78693 ,  H01L29/78696

Abstract: Disclosed is a semiconductor device including two oxide semiconductor layers, where one of the oxide semiconductor layers has an n-doped region while the other of the oxide semiconductor layers is substantially i-type. The semiconductor device includes the two oxide semiconductor layers sandwiched between a pair of oxide layers which have a common element included in any of the two oxide semiconductor layers. A double-well structure is formed in a region including the two oxide semiconductor layers and the pair of oxide layers, leading to the formation of a channel formation region in the n-doped region. This structure allows the channel formation region to be surrounded by an i-type oxide semiconductor, which contributes to the production of a semiconductor device that is capable of feeding enormous current.

Abstract translation: 公开了包括两个氧化物半导体层的半导体器件，其中氧化物半导体层中的一个具有n掺杂区域，而另一个氧化物半导体层基本上是i型。 半导体器件包括夹在一对氧化物层之间的两个氧化物半导体层，其具有包含在两个氧化物半导体层中的任一个中的共同元素。 在包括两个氧化物半导体层和一对氧化物层的区域中形成双阱结构，导致在n掺杂区域中形成沟道形成区域。 该结构允许沟道形成区域被i型氧化物半导体包围，这有助于生产能够馈送大量电流的半导体器件。

公开(公告)号：US20160240685A1

公开(公告)日：2016-08-18

申请号：US15138539

申请日：2016-04-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA

IPC: H01L29/786 ,  H01L23/532 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L23/53257 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/66969 ,  H01L29/78

Abstract: In a semiconductor device including a transistor, an oxygen release type oxide insulating film is formed in contact with a channel formation region of the transistor. The channel formation region is formed in an oxide semiconductor film. Oxygen is supplied from the oxide insulating film to the oxide semiconductor film. Further, an oxygen barrier film which penetrates the oxide insulating film is formed around the channel formation region, whereby a diffusion of oxygen to the wiring, the electrode, and the like connected to the transistor can be suppressed.

Abstract translation: 在包括晶体管的半导体器件中，形成与晶体管的沟道形成区域接触的氧释放型氧化物绝缘膜。 沟道形成区形成在氧化物半导体膜中。 从氧化物绝缘膜向氧化物半导体膜供给氧。 此外，在沟道形成区域周围形成穿透氧化物绝缘膜的氧阻隔膜，由此可以抑制氧与连接到晶体管的布线，电极等的扩散。

公开(公告)号：US20160190338A1

公开(公告)日：2016-06-30

申请号：US14976474

申请日：2015-12-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Daisuke MATSUBAYASHI ,  Kazuki TANEMURA

IPC: H01L29/786 ,  H01L21/479 ,  H01L27/12

CPC classification number: H01L29/78606 ,  H01L21/479 ,  H01L27/1225 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42384 ,  H01L29/66833 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/7883 ,  H01L29/792

Abstract: To provide a semiconductor device suitable for high reliability and high-speed operation. The semiconductor device includes a first conductor, a first insulator, a second insulator, a semiconductor, and an electron trap layer. The semiconductor includes a channel formation region. The first conductor includes a region overlapping with the channel formation region with the first insulator provided therebetween. The second insulator is placed to include a region in contact with a side surface of the first conductor. The electron trap layer is placed to face the first conductor with the second insulator provided therebetween.

Abstract translation: 提供适用于高可靠性和高速运行的半导体器件。 半导体器件包括第一导体，第一绝缘体，第二绝缘体，半导体和电子陷阱层。 半导体包括沟道形成区域。 第一导体包括与沟道形成区重叠的区域，其间设置有第一绝缘体。 第二绝缘体被放置成包括与第一导体的侧表面接触的区域。 电子陷阱层被放置为面对第一导体，其间设置有第二绝缘体。

公开(公告)号：US20160172500A1

公开(公告)日：2016-06-16

申请号：US14963945

申请日：2015-12-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Tetsuhiro TANAKA ,  Akihisa SHIMOMURA ,  Yasumasa YAMANE ,  Ryo TOKUMARU ,  Yuhei SATO ,  Kazuhiro TSUTSUI

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/7869 ,  C23C14/08 ,  C23C14/3414 ,  H01L21/02266 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A transistor with stable electrical characteristics is provided. The transistor includes a first insulator over a substrate; first to third oxide insulators over the first insulator; a second insulator over the third oxide insulator; a first conductor over the second insulator; and a third insulator over the first conductor. An energy level of a conduction band minimum of each of the first and second oxide insulators is closer to a vacuum level than that of the oxide semiconductor is. An energy level of a conduction band minimum of the third oxide insulator is closer to the vacuum level than that of the second oxide insulator is. The first insulator contains oxygen. The number of oxygen molecules released from the first insulator measured by thermal desorption spectroscopy is greater than or equal to 1E14 molecules/cm2 and less than or equal to 1E16 molecules/cm2.

Abstract translation: 提供具有稳定电特性的晶体管。 晶体管包括在衬底上的第一绝缘体; 第一绝缘子上的第一至第三绝缘体; 在所述第三氧化物绝缘体上的第二绝缘体; 第二绝缘体上的第一导体; 以及在第一导体上的第三绝缘体。 每个第一和第二氧化物绝缘体的导带最小值的能级比氧化物半导体的能级更接近真空度。 第三氧化物绝缘体的导带最小值的能级比第二氧化物绝缘体的能级更接近真空度。 第一绝缘体包含氧。 通过热解吸光谱测定从第一绝缘体释放的氧分子的数量大于或等于1E14分子/ cm 2且小于或等于1E16分子/ cm 2。

公开(公告)号：US20160049521A1

公开(公告)日：2016-02-18

申请号：US14926737

申请日：2015-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sachiaki TEZUKA ,  Hideomi SUZAWA ,  Akihisa SHIMOMURA ,  Tetsuhiro TANAKA

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/0234 ,  H01L29/247 ,  H01L29/66969 ,  H01L29/78693

Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided. Oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer to a channel formation region, whereby oxygen vacancies which might be generated in the channel formation region are filled. Further, a protective insulating layer containing a small amount of hydrogen and functioning as a barrier layer having a low permeability to oxygen is formed over the gate electrode layer so as to cover side surfaces of an oxide layer and a gate insulating layer that are provided over the oxide semiconductor layer, whereby release of oxygen from the gate insulating layer and/or the oxide layer is prevented and generation of oxygen vacancies in a channel formation region is prevented.

Abstract translation: 提供了包括氧化物半导体的高度可靠的半导体器件。 氧气从设置在氧化物半导体层下方的基底绝缘层供给到沟道形成区域，由此填充可能在沟道形成区域中产生的氧空位。 此外，在栅电极层上形成包含少量氢并用作具有低氧渗透性的阻挡层的保护绝缘层，以覆盖设置在氧化物层和栅绝缘层上的侧表面 氧化物半导体层，从而防止了从栅极绝缘层和/或氧化物层的氧的释放，并且防止了沟道形成区域中的氧空位的产生。

公开(公告)号：US20150236166A1

公开(公告)日：2015-08-20

申请号：US14700528

申请日：2015-04-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Tetsuhiro TANAKA ,  Junichi KOEZUKA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L29/66969

Abstract: Provided is a miniaturized transistor with stable and high electrical characteristics with high yield. In a semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in this order, a first sidewall insulating layer is provided in contact with a side surface of the gate electrode layer, and a second sidewall insulating layer is provided to cover a side surface of the first sidewall insulating layer. The first sidewall insulating layer is an aluminum oxide film in which a crevice with an even shape is formed on its side surface. The second sidewall insulating layer is provided to cover the crevice. A source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the second sidewall insulating layer.

Abstract translation: 提供了一种具有稳定和高电特性并且高产率的小型化晶体管。 在包括依次层叠有氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管的半导体装置中，设置与栅电极层的侧面接触的第一侧壁绝缘层， 提供第二侧壁绝缘层以覆盖第一侧壁绝缘层的侧表面。 第一侧壁绝缘层是在其侧表面上形成具有均匀形状的缝隙的氧化铝膜。 第二侧壁绝缘层设置成覆盖缝隙。 源电极层和漏电极层设置成与氧化物半导体膜和第二侧壁绝缘层接触。

公开(公告)号：US20150162449A1

公开(公告)日：2015-06-11

申请号：US14620403

申请日：2015-02-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiromichi GODO ,  Tetsuhiro TANAKA

IPC: H01L29/786 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/4908

Abstract: To reduce oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film and to improve electric characteristics of a transistor including the oxide semiconductor film. A semiconductor device includes a gate electrode whose Gibbs free energy for oxidation is higher than that of a gate insulating film. In a region where the gate electrode is in contact with the gate insulating film, oxygen moves from the gate electrode to the gate insulating film, which is caused because the gate electrode has higher Gibbs free energy for oxidation than the gate insulating film. The oxygen passes through the gate insulating film and is supplied to the oxide semiconductor film in contact with the gate insulating film, whereby oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced.

Abstract translation: 为了减少氧化物半导体膜和氧化物半导体膜附近的氧空位，并且改善包括氧化物半导体膜的晶体管的电特性。 半导体器件包括栅极电极，其吉布斯自由能用于氧化，高于栅极绝缘膜的自由能。 在栅电极与栅极绝缘膜接触的区域中，由于栅电极具有比栅极绝缘膜更高的吉布斯自由能进行氧化而引起的氧从栅电极移动到栅极绝缘膜。 氧气通过栅极绝缘膜，并且被提供给与栅极绝缘膜接触的氧化物半导体膜，由此可以减少氧化物半导体膜中的氧空位和氧化物半导体膜附近的氧空位。

公开(公告)号：US20150084044A1

公开(公告)日：2015-03-26

申请号：US14486179

申请日：2014-09-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Toshihiko TAKEUCHI ,  Yasumasa YAMANE

IPC: H01L29/06 ,  H01L29/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/0607 ,  H01L29/12 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/78696

Abstract: Provided is a semiconductor device having a structure with which a decrease in electrical characteristics that becomes more significant with miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film, a gate electrode overlapping with the first oxide semiconductor film, a first gate insulating film between the first oxide semiconductor film and the gate electrode, and a second gate insulating film between the first gate insulating film and the gate electrode. In the first gate insulating film, a peak appears at a diffraction angle 2θ of around 28° by X-ray diffraction. A band gap of the first oxide semiconductor film is smaller than a band gap of the first gate insulating film, and the band gap of the first gate insulating film is smaller than a band gap of the second gate insulating film.

Abstract translation: 提供一种半导体器件，其具有可以抑制随着小型化而变得更显着的电特性的降低的结构。 半导体器件包括第一氧化物半导体膜，与第一氧化物半导体膜重叠的栅电极，第一氧化物半导体膜和栅极之间的第一栅极绝缘膜，以及在第一栅极绝缘膜和第二栅极绝缘膜之间的第二栅极绝缘膜 栅电极。 在第一栅极绝缘膜中，以衍射角2出现峰值; 通过X射线衍射测得约为28°。 第一氧化物半导体膜的带隙小于第一栅极绝缘膜的带隙，第一栅极绝缘膜的带隙小于第二栅极绝缘膜的带隙。

公开(公告)号：US20150069385A1

公开(公告)日：2015-03-12

申请号：US14476767

申请日：2014-09-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L29/7869 ,  G11C7/04 ,  G11C11/24 ,  G11C14/0054 ,  G11C16/0466 ,  G11C16/3404 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/7881

Abstract: A method for adjusting threshold of a semiconductor device is provided. In a plurality of semiconductor devices each including a semiconductor, a source or drain electrode electrically in contact with the semiconductor, a gate electrode, and a charge trap layer between a gate electrode and the semiconductor, a state where the potential of the gate electrode is set higher than the potential of the source or drain electrode while the semiconductor devices are heated at 150° C. or higher and 300° C. or lower is kept for one second or longer to trap electrons in the charge trap layer, so that the threshold is increased and Icut is reduced. Here, the potential difference between the gate electrode and the source or drain electrode is set so that it is different between the semiconductor devices, and the thresholds of the semiconductor devices are adjusted to be appropriate to each purpose.

Abstract translation: 提供了一种用于调整半导体器件的阈值的方法。 在多个半导体器件中，每个半导体器件包括半导体，与半导体电接触的源极或漏极，栅电极和栅电极与半导体之间的电荷陷阱层，栅电极的电位为 设定为高于源极或漏极的电位，同时将半导体器件在150℃以上且300℃以下的温度加热保持1秒以上以在电荷陷阱层中捕获电子，使得 阈值增加并且Icut减小。 这里，栅电极和源电极或漏电极之间的电位差被设定为在半导体器件之间不同，并且将半导体器件的阈值调整为适合于每个目的。